RTOS 1.0
stm32f413xx.h
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33#ifndef __STM32F413xx_H
34#define __STM32F413xx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
95 ADC_IRQn = 18,
154 RNG_IRQn = 80,
155 FPU_IRQn = 81,
171} IRQn_Type;
172
176
177#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
178#include "system_stm32f4xx.h"
179#include <stdint.h>
180
184
188
189typedef struct
190{
191 __IO uint32_t SR;
192 __IO uint32_t CR1;
193 __IO uint32_t CR2;
194 __IO uint32_t SMPR1;
195 __IO uint32_t SMPR2;
196 __IO uint32_t JOFR1;
197 __IO uint32_t JOFR2;
198 __IO uint32_t JOFR3;
199 __IO uint32_t JOFR4;
200 __IO uint32_t HTR;
201 __IO uint32_t LTR;
202 __IO uint32_t SQR1;
203 __IO uint32_t SQR2;
204 __IO uint32_t SQR3;
205 __IO uint32_t JSQR;
206 __IO uint32_t JDR1;
207 __IO uint32_t JDR2;
208 __IO uint32_t JDR3;
209 __IO uint32_t JDR4;
210 __IO uint32_t DR;
212
213typedef struct
214{
215 __IO uint32_t CSR;
216 __IO uint32_t CCR;
217 __IO uint32_t CDR;
220
221
225
226typedef struct
227{
228 __IO uint32_t TIR;
229 __IO uint32_t TDTR;
230 __IO uint32_t TDLR;
231 __IO uint32_t TDHR;
233
237
238typedef struct
239{
240 __IO uint32_t RIR;
241 __IO uint32_t RDTR;
242 __IO uint32_t RDLR;
243 __IO uint32_t RDHR;
245
249
250typedef struct
251{
252 __IO uint32_t FR1;
253 __IO uint32_t FR2;
255
259
260typedef struct
261{
262 __IO uint32_t MCR;
263 __IO uint32_t MSR;
264 __IO uint32_t TSR;
265 __IO uint32_t RF0R;
266 __IO uint32_t RF1R;
267 __IO uint32_t IER;
268 __IO uint32_t ESR;
269 __IO uint32_t BTR;
270 uint32_t RESERVED0[88];
271 CAN_TxMailBox_TypeDef sTxMailBox[3];
272 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
273 uint32_t RESERVED1[12];
274 __IO uint32_t FMR;
275 __IO uint32_t FM1R;
276 uint32_t RESERVED2;
277 __IO uint32_t FS1R;
278 uint32_t RESERVED3;
279 __IO uint32_t FFA1R;
280 uint32_t RESERVED4;
281 __IO uint32_t FA1R;
282 uint32_t RESERVED5[8];
283 CAN_FilterRegister_TypeDef sFilterRegister[28];
285
289
290typedef struct
291{
292 __IO uint32_t DR;
293 __IO uint8_t IDR;
294 uint8_t RESERVED0;
295 uint16_t RESERVED1;
296 __IO uint32_t CR;
298
302typedef struct
303{
304 __IO uint32_t FLTCR1;
305 __IO uint32_t FLTCR2;
306 __IO uint32_t FLTISR;
307 __IO uint32_t FLTICR;
308 __IO uint32_t FLTJCHGR;
309 __IO uint32_t FLTFCR;
310 __IO uint32_t FLTJDATAR;
311 __IO uint32_t FLTRDATAR;
312 __IO uint32_t FLTAWHTR;
313 __IO uint32_t FLTAWLTR;
314 __IO uint32_t FLTAWSR;
315 __IO uint32_t FLTAWCFR;
316 __IO uint32_t FLTEXMAX;
317 __IO uint32_t FLTEXMIN;
318 __IO uint32_t FLTCNVTIMR;
320
324typedef struct
325{
326 __IO uint32_t CHCFGR1;
327 __IO uint32_t CHCFGR2;
328 __IO uint32_t CHAWSCDR;
330 __IO uint32_t CHWDATAR;
331 __IO uint32_t CHDATINR;
333
337
338typedef struct
339{
340 __IO uint32_t CR;
341 __IO uint32_t SWTRIGR;
342 __IO uint32_t DHR12R1;
343 __IO uint32_t DHR12L1;
344 __IO uint32_t DHR8R1;
345 __IO uint32_t DHR12R2;
346 __IO uint32_t DHR12L2;
347 __IO uint32_t DHR8R2;
348 __IO uint32_t DHR12RD;
349 __IO uint32_t DHR12LD;
350 __IO uint32_t DHR8RD;
351 __IO uint32_t DOR1;
352 __IO uint32_t DOR2;
353 __IO uint32_t SR;
355
359
360typedef struct
361{
362 __IO uint32_t IDCODE;
363 __IO uint32_t CR;
364 __IO uint32_t APB1FZ;
365 __IO uint32_t APB2FZ;
367
368
372
373typedef struct
374{
375 __IO uint32_t CR;
376 __IO uint32_t NDTR;
377 __IO uint32_t PAR;
378 __IO uint32_t M0AR;
379 __IO uint32_t M1AR;
380 __IO uint32_t FCR;
382
383typedef struct
384{
385 __IO uint32_t LISR;
386 __IO uint32_t HISR;
387 __IO uint32_t LIFCR;
388 __IO uint32_t HIFCR;
390
394
395typedef struct
396{
397 __IO uint32_t IMR;
398 __IO uint32_t EMR;
399 __IO uint32_t RTSR;
400 __IO uint32_t FTSR;
401 __IO uint32_t SWIER;
402 __IO uint32_t PR;
404
408
409typedef struct
410{
411 __IO uint32_t ACR;
412 __IO uint32_t KEYR;
413 __IO uint32_t OPTKEYR;
414 __IO uint32_t SR;
415 __IO uint32_t CR;
416 __IO uint32_t OPTCR;
417 __IO uint32_t OPTCR1;
419
420
421
425
426typedef struct
427{
428 __IO uint32_t BTCR[8];
430
434
435typedef struct
436{
437 __IO uint32_t BWTR[7];
442
443typedef struct
444{
445 __IO uint32_t MODER;
446 __IO uint32_t OTYPER;
447 __IO uint32_t OSPEEDR;
448 __IO uint32_t PUPDR;
449 __IO uint32_t IDR;
450 __IO uint32_t ODR;
451 __IO uint32_t BSRR;
452 __IO uint32_t LCKR;
453 __IO uint32_t AFR[2];
455
459
460typedef struct
461{
462 __IO uint32_t MEMRMP;
463 __IO uint32_t PMC;
464 __IO uint32_t EXTICR[4];
465 uint32_t RESERVED;
466 __IO uint32_t CFGR2;
467 __IO uint32_t CMPCR;
468 uint32_t RESERVED1[2];
469 __IO uint32_t CFGR;
470 __IO uint32_t MCHDLYCR;
472
476
477typedef struct
478{
479 __IO uint32_t CR1;
480 __IO uint32_t CR2;
481 __IO uint32_t OAR1;
482 __IO uint32_t OAR2;
483 __IO uint32_t DR;
484 __IO uint32_t SR1;
485 __IO uint32_t SR2;
486 __IO uint32_t CCR;
487 __IO uint32_t TRISE;
488 __IO uint32_t FLTR;
490
494
495typedef struct
496{
497 __IO uint32_t CR1;
498 __IO uint32_t CR2;
499 __IO uint32_t OAR1;
500 __IO uint32_t OAR2;
501 __IO uint32_t TIMINGR;
502 __IO uint32_t TIMEOUTR;
503 __IO uint32_t ISR;
504 __IO uint32_t ICR;
505 __IO uint32_t PECR;
506 __IO uint32_t RXDR;
507 __IO uint32_t TXDR;
509
513
514typedef struct
515{
516 __IO uint32_t KR;
517 __IO uint32_t PR;
518 __IO uint32_t RLR;
519 __IO uint32_t SR;
521
522
526
527typedef struct
528{
529 __IO uint32_t CR;
530 __IO uint32_t CSR;
532
536
537typedef struct
538{
539 __IO uint32_t CR;
540 __IO uint32_t PLLCFGR;
541 __IO uint32_t CFGR;
542 __IO uint32_t CIR;
543 __IO uint32_t AHB1RSTR;
544 __IO uint32_t AHB2RSTR;
545 __IO uint32_t AHB3RSTR;
546 uint32_t RESERVED0;
547 __IO uint32_t APB1RSTR;
548 __IO uint32_t APB2RSTR;
549 uint32_t RESERVED1[2];
550 __IO uint32_t AHB1ENR;
551 __IO uint32_t AHB2ENR;
552 __IO uint32_t AHB3ENR;
553 uint32_t RESERVED2;
554 __IO uint32_t APB1ENR;
555 __IO uint32_t APB2ENR;
556 uint32_t RESERVED3[2];
557 __IO uint32_t AHB1LPENR;
558 __IO uint32_t AHB2LPENR;
559 __IO uint32_t AHB3LPENR;
560 uint32_t RESERVED4;
561 __IO uint32_t APB1LPENR;
562 __IO uint32_t APB2LPENR;
563 uint32_t RESERVED5[2];
564 __IO uint32_t BDCR;
565 __IO uint32_t CSR;
566 uint32_t RESERVED6[2];
567 __IO uint32_t SSCGR;
568 __IO uint32_t PLLI2SCFGR;
569 uint32_t RESERVED7;
570 __IO uint32_t DCKCFGR;
571 __IO uint32_t CKGATENR;
572 __IO uint32_t DCKCFGR2;
574
578
579typedef struct
580{
581 __IO uint32_t TR;
582 __IO uint32_t DR;
583 __IO uint32_t CR;
584 __IO uint32_t ISR;
585 __IO uint32_t PRER;
586 __IO uint32_t WUTR;
587 __IO uint32_t CALIBR;
588 __IO uint32_t ALRMAR;
589 __IO uint32_t ALRMBR;
590 __IO uint32_t WPR;
591 __IO uint32_t SSR;
592 __IO uint32_t SHIFTR;
593 __IO uint32_t TSTR;
594 __IO uint32_t TSDR;
595 __IO uint32_t TSSSR;
596 __IO uint32_t CALR;
597 __IO uint32_t TAFCR;
598 __IO uint32_t ALRMASSR;
599 __IO uint32_t ALRMBSSR;
600 uint32_t RESERVED7;
601 __IO uint32_t BKP0R;
602 __IO uint32_t BKP1R;
603 __IO uint32_t BKP2R;
604 __IO uint32_t BKP3R;
605 __IO uint32_t BKP4R;
606 __IO uint32_t BKP5R;
607 __IO uint32_t BKP6R;
608 __IO uint32_t BKP7R;
609 __IO uint32_t BKP8R;
610 __IO uint32_t BKP9R;
611 __IO uint32_t BKP10R;
612 __IO uint32_t BKP11R;
613 __IO uint32_t BKP12R;
614 __IO uint32_t BKP13R;
615 __IO uint32_t BKP14R;
616 __IO uint32_t BKP15R;
617 __IO uint32_t BKP16R;
618 __IO uint32_t BKP17R;
619 __IO uint32_t BKP18R;
620 __IO uint32_t BKP19R;
622
626
627typedef struct
628{
629 __IO uint32_t GCR;
631
632typedef struct
633{
634 __IO uint32_t CR1;
635 __IO uint32_t CR2;
636 __IO uint32_t FRCR;
637 __IO uint32_t SLOTR;
638 __IO uint32_t IMR;
639 __IO uint32_t SR;
640 __IO uint32_t CLRFR;
641 __IO uint32_t DR;
643
647
648typedef struct
649{
650 __IO uint32_t POWER;
651 __IO uint32_t CLKCR;
652 __IO uint32_t ARG;
653 __IO uint32_t CMD;
654 __IO const uint32_t RESPCMD;
655 __IO const uint32_t RESP1;
656 __IO const uint32_t RESP2;
657 __IO const uint32_t RESP3;
658 __IO const uint32_t RESP4;
659 __IO uint32_t DTIMER;
660 __IO uint32_t DLEN;
661 __IO uint32_t DCTRL;
662 __IO const uint32_t DCOUNT;
663 __IO const uint32_t STA;
664 __IO uint32_t ICR;
665 __IO uint32_t MASK;
666 uint32_t RESERVED0[2];
667 __IO const uint32_t FIFOCNT;
668 uint32_t RESERVED1[13];
669 __IO uint32_t FIFO;
671
675
676typedef struct
677{
678 __IO uint32_t CR1;
679 __IO uint32_t CR2;
680 __IO uint32_t SR;
681 __IO uint32_t DR;
682 __IO uint32_t CRCPR;
683 __IO uint32_t RXCRCR;
684 __IO uint32_t TXCRCR;
685 __IO uint32_t I2SCFGR;
686 __IO uint32_t I2SPR;
688
692
693typedef struct
694{
695 __IO uint32_t CR;
696 __IO uint32_t DCR;
697 __IO uint32_t SR;
698 __IO uint32_t FCR;
699 __IO uint32_t DLR;
700 __IO uint32_t CCR;
701 __IO uint32_t AR;
702 __IO uint32_t ABR;
703 __IO uint32_t DR;
704 __IO uint32_t PSMKR;
705 __IO uint32_t PSMAR;
706 __IO uint32_t PIR;
707 __IO uint32_t LPTR;
709
713
714typedef struct
715{
716 __IO uint32_t CR1;
717 __IO uint32_t CR2;
718 __IO uint32_t SMCR;
719 __IO uint32_t DIER;
720 __IO uint32_t SR;
721 __IO uint32_t EGR;
722 __IO uint32_t CCMR1;
723 __IO uint32_t CCMR2;
724 __IO uint32_t CCER;
725 __IO uint32_t CNT;
726 __IO uint32_t PSC;
727 __IO uint32_t ARR;
728 __IO uint32_t RCR;
729 __IO uint32_t CCR1;
730 __IO uint32_t CCR2;
731 __IO uint32_t CCR3;
732 __IO uint32_t CCR4;
733 __IO uint32_t BDTR;
734 __IO uint32_t DCR;
735 __IO uint32_t DMAR;
736 __IO uint32_t OR;
738
742
743typedef struct
744{
745 __IO uint32_t SR;
746 __IO uint32_t DR;
747 __IO uint32_t BRR;
748 __IO uint32_t CR1;
749 __IO uint32_t CR2;
750 __IO uint32_t CR3;
751 __IO uint32_t GTPR;
753
757
758typedef struct
759{
760 __IO uint32_t CR;
761 __IO uint32_t CFR;
762 __IO uint32_t SR;
764
768
769typedef struct
770{
771 __IO uint32_t CR;
772 __IO uint32_t SR;
773 __IO uint32_t DR;
775
779typedef struct
780{
781 __IO uint32_t GOTGCTL;
782 __IO uint32_t GOTGINT;
783 __IO uint32_t GAHBCFG;
784 __IO uint32_t GUSBCFG;
785 __IO uint32_t GRSTCTL;
786 __IO uint32_t GINTSTS;
787 __IO uint32_t GINTMSK;
788 __IO uint32_t GRXSTSR;
789 __IO uint32_t GRXSTSP;
790 __IO uint32_t GRXFSIZ;
791 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
792 __IO uint32_t HNPTXSTS;
793 uint32_t Reserved30[2];
794 __IO uint32_t GCCFG;
795 __IO uint32_t CID;
796 uint32_t Reserved5[3];
797 __IO uint32_t GHWCFG3;
798 uint32_t Reserved6;
799 __IO uint32_t GLPMCFG;
800 uint32_t Reserved;
801 __IO uint32_t GDFIFOCFG;
802 uint32_t Reserved43[40];
803 __IO uint32_t HPTXFSIZ;
804 __IO uint32_t DIEPTXF[0x0F];
806
810typedef struct
811{
812 __IO uint32_t DCFG;
813 __IO uint32_t DCTL;
814 __IO uint32_t DSTS;
815 uint32_t Reserved0C;
816 __IO uint32_t DIEPMSK;
817 __IO uint32_t DOEPMSK;
818 __IO uint32_t DAINT;
819 __IO uint32_t DAINTMSK;
820 uint32_t Reserved20;
821 uint32_t Reserved9;
822 __IO uint32_t DVBUSDIS;
823 __IO uint32_t DVBUSPULSE;
824 __IO uint32_t DTHRCTL;
825 __IO uint32_t DIEPEMPMSK;
826 __IO uint32_t DEACHINT;
827 __IO uint32_t DEACHMSK;
828 uint32_t Reserved40;
829 __IO uint32_t DINEP1MSK;
830 uint32_t Reserved44[15];
831 __IO uint32_t DOUTEP1MSK;
833
837typedef struct
838{
839 __IO uint32_t DIEPCTL;
840 uint32_t Reserved04;
841 __IO uint32_t DIEPINT;
842 uint32_t Reserved0C;
843 __IO uint32_t DIEPTSIZ;
844 __IO uint32_t DIEPDMA;
845 __IO uint32_t DTXFSTS;
846 uint32_t Reserved18;
848
852typedef struct
853{
854 __IO uint32_t DOEPCTL;
855 uint32_t Reserved04;
856 __IO uint32_t DOEPINT;
857 uint32_t Reserved0C;
858 __IO uint32_t DOEPTSIZ;
859 __IO uint32_t DOEPDMA;
860 uint32_t Reserved18[2];
862
866typedef struct
867{
868 __IO uint32_t HCFG;
869 __IO uint32_t HFIR;
870 __IO uint32_t HFNUM;
871 uint32_t Reserved40C;
872 __IO uint32_t HPTXSTS;
873 __IO uint32_t HAINT;
874 __IO uint32_t HAINTMSK;
876
880typedef struct
881{
882 __IO uint32_t HCCHAR;
883 __IO uint32_t HCSPLT;
884 __IO uint32_t HCINT;
885 __IO uint32_t HCINTMSK;
886 __IO uint32_t HCTSIZ;
887 __IO uint32_t HCDMA;
888 uint32_t Reserved[2];
890
894typedef struct
895{
896 __IO uint32_t ISR;
897 __IO uint32_t ICR;
898 __IO uint32_t IER;
899 __IO uint32_t CFGR;
900 __IO uint32_t CR;
901 __IO uint32_t CMP;
902 __IO uint32_t ARR;
903 __IO uint32_t CNT;
904 __IO uint32_t OR;
906
910
914#define FLASH_BASE 0x08000000UL
915#define SRAM1_BASE 0x20000000UL
916#define SRAM2_BASE 0x20040000UL
917#define PERIPH_BASE 0x40000000UL
918#define FSMC_R_BASE 0xA0000000UL
919#define QSPI_R_BASE 0xA0001000UL
920#define SRAM1_BB_BASE 0x22000000UL
921#define SRAM2_BB_BASE 0x22800000UL
922#define PERIPH_BB_BASE 0x42000000UL
923#define FLASH_END 0x0817FFFFUL
924#define FLASH_OTP_BASE 0x1FFF7800UL
925#define FLASH_OTP_END 0x1FFF7A0FUL
926
927/* Legacy defines */
928#define SRAM_BASE SRAM1_BASE
929#define SRAM_BB_BASE SRAM1_BB_BASE
930
932#define APB1PERIPH_BASE PERIPH_BASE
933#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
934#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
935#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
936
938#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
939#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
940#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
941#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
942#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
943#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
944#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
945#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
946#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
947#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
948#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
949#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
950#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
951#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
952#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
953#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
954#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
955#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
956#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
957#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
958#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
959#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
960#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
961#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
962#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
963#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
964#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
965#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
966#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
967#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
968#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
969#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
970
972#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
973#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
974#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
975#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
976#define UART9_BASE (APB2PERIPH_BASE + 0x1800UL)
977#define UART10_BASE (APB2PERIPH_BASE + 0x1C00UL)
978#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
979#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
980/* Legacy define */
981#define ADC_BASE ADC1_COMMON_BASE
982#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
983#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
984#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
985#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
986#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
987#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
988#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
989#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
990#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
991#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
992#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400UL)
993#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
994#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
995#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
996#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
997#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
998#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
999#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
1000#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
1001#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40UL)
1002#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60UL)
1003#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80UL)
1004#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0UL)
1005#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0UL)
1006#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0UL)
1007#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100UL)
1008#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180UL)
1009#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200UL)
1010#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280UL)
1011#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1012#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1013#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1014
1016#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1017#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1018#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1019#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1020#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1021#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1022#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1023#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1024#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1025#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1026#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1027#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1028#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1029#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1030#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1031#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1032#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1033#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1034#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1035#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1036#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1037#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1038#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1039#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1040#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1041#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1042#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1043#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1044#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1045
1047#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1048
1049
1051#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
1052#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
1053
1055#define DBGMCU_BASE 0xE0042000UL
1057#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1058
1059#define USB_OTG_GLOBAL_BASE 0x000UL
1060#define USB_OTG_DEVICE_BASE 0x800UL
1061#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1062#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1063#define USB_OTG_EP_REG_SIZE 0x20UL
1064#define USB_OTG_HOST_BASE 0x400UL
1065#define USB_OTG_HOST_PORT_BASE 0x440UL
1066#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1067#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1068#define USB_OTG_PCGCCTL_BASE 0xE00UL
1069#define USB_OTG_FIFO_BASE 0x1000UL
1070#define USB_OTG_FIFO_SIZE 0x1000UL
1071
1072#define UID_BASE 0x1FFF7A10UL
1073#define FLASHSIZE_BASE 0x1FFF7A22UL
1074#define PACKAGE_BASE 0x1FFF7BF0UL
1078
1082#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1083#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1084#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1085#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1086#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1087#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1088#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1089#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1090#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1091#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1092#define RTC ((RTC_TypeDef *) RTC_BASE)
1093#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1094#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1095#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1096#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1097#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1098#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1099#define USART2 ((USART_TypeDef *) USART2_BASE)
1100#define USART3 ((USART_TypeDef *) USART3_BASE)
1101#define UART4 ((USART_TypeDef *) UART4_BASE)
1102#define UART5 ((USART_TypeDef *) UART5_BASE)
1103#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1104#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1105#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1106#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1107#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1108#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1109#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1110#define PWR ((PWR_TypeDef *) PWR_BASE)
1111#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1112#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1113#define UART7 ((USART_TypeDef *) UART7_BASE)
1114#define UART8 ((USART_TypeDef *) UART8_BASE)
1115#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1116#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1117#define USART1 ((USART_TypeDef *) USART1_BASE)
1118#define USART6 ((USART_TypeDef *) USART6_BASE)
1119#define UART9 ((USART_TypeDef *) UART9_BASE)
1120#define UART10 ((USART_TypeDef *) UART10_BASE)
1121#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1122#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1123/* Legacy define */
1124#define ADC ADC1_COMMON
1125#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1126#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1127#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1128#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1129#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1130#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1131#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1132#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1133#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1134#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1135#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1136#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1137#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1138#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1139#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1140#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
1141#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
1142#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
1143#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
1144#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
1145#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
1146#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
1147#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
1148#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
1149#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
1150#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
1151#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
1152#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1153#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1154#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1155#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1156#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1157#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1158#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1159#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1160#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1161#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1162#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1163#define CRC ((CRC_TypeDef *) CRC_BASE)
1164#define RCC ((RCC_TypeDef *) RCC_BASE)
1165#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1166#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1167#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1168#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1169#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1170#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1171#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1172#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1173#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1174#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1175#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1176#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1177#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1178#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1179#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1180#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1181#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1182#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1183#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1184#define RNG ((RNG_TypeDef *) RNG_BASE)
1185#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1186#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1187#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1188#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1189#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1190
1194
1198
1202#define LSI_STARTUP_TIME 40U
1206
1210
1211/******************************************************************************/
1212/* Peripheral Registers_Bits_Definition */
1213/******************************************************************************/
1214
1215/******************************************************************************/
1216/* */
1217/* Analog to Digital Converter */
1218/* */
1219/******************************************************************************/
1220
1221/******************** Bit definition for ADC_SR register ********************/
1222#define ADC_SR_AWD_Pos (0U)
1223#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1224#define ADC_SR_AWD ADC_SR_AWD_Msk
1225#define ADC_SR_EOC_Pos (1U)
1226#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1227#define ADC_SR_EOC ADC_SR_EOC_Msk
1228#define ADC_SR_JEOC_Pos (2U)
1229#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1230#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1231#define ADC_SR_JSTRT_Pos (3U)
1232#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1233#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1234#define ADC_SR_STRT_Pos (4U)
1235#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1236#define ADC_SR_STRT ADC_SR_STRT_Msk
1237#define ADC_SR_OVR_Pos (5U)
1238#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1239#define ADC_SR_OVR ADC_SR_OVR_Msk
1240
1241/******************* Bit definition for ADC_CR1 register ********************/
1242#define ADC_CR1_AWDCH_Pos (0U)
1243#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1244#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1245#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1246#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1247#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1248#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1249#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1250#define ADC_CR1_EOCIE_Pos (5U)
1251#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1252#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1253#define ADC_CR1_AWDIE_Pos (6U)
1254#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1255#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1256#define ADC_CR1_JEOCIE_Pos (7U)
1257#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1258#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1259#define ADC_CR1_SCAN_Pos (8U)
1260#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1261#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1262#define ADC_CR1_AWDSGL_Pos (9U)
1263#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1264#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1265#define ADC_CR1_JAUTO_Pos (10U)
1266#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1267#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1268#define ADC_CR1_DISCEN_Pos (11U)
1269#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1270#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1271#define ADC_CR1_JDISCEN_Pos (12U)
1272#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1273#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1274#define ADC_CR1_DISCNUM_Pos (13U)
1275#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1276#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1277#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1278#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1279#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1280#define ADC_CR1_JAWDEN_Pos (22U)
1281#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1282#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1283#define ADC_CR1_AWDEN_Pos (23U)
1284#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1285#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1286#define ADC_CR1_RES_Pos (24U)
1287#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1288#define ADC_CR1_RES ADC_CR1_RES_Msk
1289#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1290#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1291#define ADC_CR1_OVRIE_Pos (26U)
1292#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1293#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1294
1295/******************* Bit definition for ADC_CR2 register ********************/
1296#define ADC_CR2_ADON_Pos (0U)
1297#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1298#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1299#define ADC_CR2_CONT_Pos (1U)
1300#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1301#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1302#define ADC_CR2_DMA_Pos (8U)
1303#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1304#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1305#define ADC_CR2_DDS_Pos (9U)
1306#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1307#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1308#define ADC_CR2_EOCS_Pos (10U)
1309#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1310#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1311#define ADC_CR2_ALIGN_Pos (11U)
1312#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1313#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1314#define ADC_CR2_JEXTSEL_Pos (16U)
1315#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1316#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1317#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1318#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1319#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1320#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1321#define ADC_CR2_JEXTEN_Pos (20U)
1322#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1323#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1324#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1325#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1326#define ADC_CR2_JSWSTART_Pos (22U)
1327#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1328#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1329#define ADC_CR2_EXTSEL_Pos (24U)
1330#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1331#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1332#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1333#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1334#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1335#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1336#define ADC_CR2_EXTEN_Pos (28U)
1337#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1338#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1339#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1340#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1341#define ADC_CR2_SWSTART_Pos (30U)
1342#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1343#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1344
1345/****************** Bit definition for ADC_SMPR1 register *******************/
1346#define ADC_SMPR1_SMP10_Pos (0U)
1347#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1348#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1349#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1350#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1351#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1352#define ADC_SMPR1_SMP11_Pos (3U)
1353#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1354#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1355#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1356#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1357#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1358#define ADC_SMPR1_SMP12_Pos (6U)
1359#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1360#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1361#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1362#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1363#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1364#define ADC_SMPR1_SMP13_Pos (9U)
1365#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1366#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1367#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1368#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1369#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1370#define ADC_SMPR1_SMP14_Pos (12U)
1371#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1372#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1373#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1374#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1375#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1376#define ADC_SMPR1_SMP15_Pos (15U)
1377#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1378#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1379#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1380#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1381#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1382#define ADC_SMPR1_SMP16_Pos (18U)
1383#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1384#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1385#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1386#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1387#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1388#define ADC_SMPR1_SMP17_Pos (21U)
1389#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1390#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1391#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1392#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1393#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1394#define ADC_SMPR1_SMP18_Pos (24U)
1395#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1396#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1397#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1398#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1399#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1400
1401/****************** Bit definition for ADC_SMPR2 register *******************/
1402#define ADC_SMPR2_SMP0_Pos (0U)
1403#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1404#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1405#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1406#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1407#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1408#define ADC_SMPR2_SMP1_Pos (3U)
1409#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1410#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1411#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1412#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1413#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1414#define ADC_SMPR2_SMP2_Pos (6U)
1415#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1416#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1417#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1418#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1419#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1420#define ADC_SMPR2_SMP3_Pos (9U)
1421#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1422#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1423#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1424#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1425#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1426#define ADC_SMPR2_SMP4_Pos (12U)
1427#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1428#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1429#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1430#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1431#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1432#define ADC_SMPR2_SMP5_Pos (15U)
1433#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1434#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1435#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1436#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1437#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1438#define ADC_SMPR2_SMP6_Pos (18U)
1439#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1440#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1441#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1442#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1443#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1444#define ADC_SMPR2_SMP7_Pos (21U)
1445#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1446#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1447#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1448#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1449#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1450#define ADC_SMPR2_SMP8_Pos (24U)
1451#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1452#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1453#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1454#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1455#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1456#define ADC_SMPR2_SMP9_Pos (27U)
1457#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1458#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1459#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1460#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1461#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1462
1463/****************** Bit definition for ADC_JOFR1 register *******************/
1464#define ADC_JOFR1_JOFFSET1_Pos (0U)
1465#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1466#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1467
1468/****************** Bit definition for ADC_JOFR2 register *******************/
1469#define ADC_JOFR2_JOFFSET2_Pos (0U)
1470#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1471#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1472
1473/****************** Bit definition for ADC_JOFR3 register *******************/
1474#define ADC_JOFR3_JOFFSET3_Pos (0U)
1475#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1476#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1477
1478/****************** Bit definition for ADC_JOFR4 register *******************/
1479#define ADC_JOFR4_JOFFSET4_Pos (0U)
1480#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1481#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1482
1483/******************* Bit definition for ADC_HTR register ********************/
1484#define ADC_HTR_HT_Pos (0U)
1485#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1486#define ADC_HTR_HT ADC_HTR_HT_Msk
1487
1488/******************* Bit definition for ADC_LTR register ********************/
1489#define ADC_LTR_LT_Pos (0U)
1490#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1491#define ADC_LTR_LT ADC_LTR_LT_Msk
1492
1493/******************* Bit definition for ADC_SQR1 register *******************/
1494#define ADC_SQR1_SQ13_Pos (0U)
1495#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1496#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1497#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1498#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1499#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1500#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1501#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1502#define ADC_SQR1_SQ14_Pos (5U)
1503#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1504#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1505#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1506#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1507#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1508#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1509#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1510#define ADC_SQR1_SQ15_Pos (10U)
1511#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1512#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1513#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1514#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1515#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1516#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1517#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1518#define ADC_SQR1_SQ16_Pos (15U)
1519#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1520#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1521#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1522#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1523#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1524#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1525#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1526#define ADC_SQR1_L_Pos (20U)
1527#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1528#define ADC_SQR1_L ADC_SQR1_L_Msk
1529#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1530#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1531#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1532#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1533
1534/******************* Bit definition for ADC_SQR2 register *******************/
1535#define ADC_SQR2_SQ7_Pos (0U)
1536#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1537#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1538#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1539#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1540#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1541#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1542#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1543#define ADC_SQR2_SQ8_Pos (5U)
1544#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1545#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1546#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1547#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1548#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1549#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1550#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1551#define ADC_SQR2_SQ9_Pos (10U)
1552#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1553#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1554#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1555#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1556#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1557#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1558#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1559#define ADC_SQR2_SQ10_Pos (15U)
1560#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1561#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1562#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1563#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1564#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1565#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1566#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1567#define ADC_SQR2_SQ11_Pos (20U)
1568#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1569#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1570#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1571#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1572#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1573#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1574#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1575#define ADC_SQR2_SQ12_Pos (25U)
1576#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1577#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1578#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1579#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1580#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1581#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1582#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1583
1584/******************* Bit definition for ADC_SQR3 register *******************/
1585#define ADC_SQR3_SQ1_Pos (0U)
1586#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1587#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1588#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1589#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1590#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1591#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1592#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1593#define ADC_SQR3_SQ2_Pos (5U)
1594#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1595#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1596#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1597#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1598#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1599#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1600#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1601#define ADC_SQR3_SQ3_Pos (10U)
1602#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1603#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1604#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1605#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1606#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1607#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1608#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1609#define ADC_SQR3_SQ4_Pos (15U)
1610#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1611#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1612#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1613#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1614#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1615#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1616#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1617#define ADC_SQR3_SQ5_Pos (20U)
1618#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1619#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1620#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1621#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1622#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1623#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1624#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1625#define ADC_SQR3_SQ6_Pos (25U)
1626#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1627#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1628#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1629#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1630#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1631#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1632#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1633
1634/******************* Bit definition for ADC_JSQR register *******************/
1635#define ADC_JSQR_JSQ1_Pos (0U)
1636#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1637#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1638#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1639#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1640#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1641#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1642#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1643#define ADC_JSQR_JSQ2_Pos (5U)
1644#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1645#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1646#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1647#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1648#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1649#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1650#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1651#define ADC_JSQR_JSQ3_Pos (10U)
1652#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1653#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1654#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1655#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1656#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1657#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1658#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1659#define ADC_JSQR_JSQ4_Pos (15U)
1660#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1661#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1662#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1663#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1664#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1665#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1666#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1667#define ADC_JSQR_JL_Pos (20U)
1668#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1669#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1670#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1671#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1672
1673/******************* Bit definition for ADC_JDR1 register *******************/
1674#define ADC_JDR1_JDATA_Pos (0U)
1675#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1676#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1677
1678/******************* Bit definition for ADC_JDR2 register *******************/
1679#define ADC_JDR2_JDATA_Pos (0U)
1680#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1681#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1682
1683/******************* Bit definition for ADC_JDR3 register *******************/
1684#define ADC_JDR3_JDATA_Pos (0U)
1685#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1686#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1687
1688/******************* Bit definition for ADC_JDR4 register *******************/
1689#define ADC_JDR4_JDATA_Pos (0U)
1690#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1691#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1692
1693/******************** Bit definition for ADC_DR register ********************/
1694#define ADC_DR_DATA_Pos (0U)
1695#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1696#define ADC_DR_DATA ADC_DR_DATA_Msk
1697#define ADC_DR_ADC2DATA_Pos (16U)
1698#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1699#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1700
1701/******************* Bit definition for ADC_CSR register ********************/
1702#define ADC_CSR_AWD1_Pos (0U)
1703#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1704#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1705#define ADC_CSR_EOC1_Pos (1U)
1706#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1707#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1708#define ADC_CSR_JEOC1_Pos (2U)
1709#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1710#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1711#define ADC_CSR_JSTRT1_Pos (3U)
1712#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1713#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1714#define ADC_CSR_STRT1_Pos (4U)
1715#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1716#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1717#define ADC_CSR_OVR1_Pos (5U)
1718#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1719#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1720
1721/* Legacy defines */
1722#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1723
1724/******************* Bit definition for ADC_CCR register ********************/
1725#define ADC_CCR_MULTI_Pos (0U)
1726#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1727#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1728#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1729#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1730#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1731#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1732#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1733#define ADC_CCR_DELAY_Pos (8U)
1734#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1735#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1736#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1737#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1738#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1739#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1740#define ADC_CCR_DDS_Pos (13U)
1741#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1742#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1743#define ADC_CCR_DMA_Pos (14U)
1744#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1745#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1746#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1747#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1748#define ADC_CCR_ADCPRE_Pos (16U)
1749#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1750#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1751#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1752#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1753#define ADC_CCR_VBATE_Pos (22U)
1754#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1755#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1756#define ADC_CCR_TSVREFE_Pos (23U)
1757#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1758#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1759
1760/******************* Bit definition for ADC_CDR register ********************/
1761#define ADC_CDR_DATA1_Pos (0U)
1762#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1763#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1764#define ADC_CDR_DATA2_Pos (16U)
1765#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1766#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1767
1768/* Legacy defines */
1769#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1770#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1771
1772/******************************************************************************/
1773/* */
1774/* Controller Area Network */
1775/* */
1776/******************************************************************************/
1778/******************* Bit definition for CAN_MCR register ********************/
1779#define CAN_MCR_INRQ_Pos (0U)
1780#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1781#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1782#define CAN_MCR_SLEEP_Pos (1U)
1783#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1784#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1785#define CAN_MCR_TXFP_Pos (2U)
1786#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1787#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1788#define CAN_MCR_RFLM_Pos (3U)
1789#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1790#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1791#define CAN_MCR_NART_Pos (4U)
1792#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1793#define CAN_MCR_NART CAN_MCR_NART_Msk
1794#define CAN_MCR_AWUM_Pos (5U)
1795#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1796#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1797#define CAN_MCR_ABOM_Pos (6U)
1798#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1799#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1800#define CAN_MCR_TTCM_Pos (7U)
1801#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1802#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1803#define CAN_MCR_RESET_Pos (15U)
1804#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1805#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1806#define CAN_MCR_DBF_Pos (16U)
1807#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1808#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1809/******************* Bit definition for CAN_MSR register ********************/
1810#define CAN_MSR_INAK_Pos (0U)
1811#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1812#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1813#define CAN_MSR_SLAK_Pos (1U)
1814#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1815#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1816#define CAN_MSR_ERRI_Pos (2U)
1817#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1818#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1819#define CAN_MSR_WKUI_Pos (3U)
1820#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1821#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1822#define CAN_MSR_SLAKI_Pos (4U)
1823#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1824#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1825#define CAN_MSR_TXM_Pos (8U)
1826#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1827#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1828#define CAN_MSR_RXM_Pos (9U)
1829#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1830#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1831#define CAN_MSR_SAMP_Pos (10U)
1832#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1833#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1834#define CAN_MSR_RX_Pos (11U)
1835#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1836#define CAN_MSR_RX CAN_MSR_RX_Msk
1837
1838/******************* Bit definition for CAN_TSR register ********************/
1839#define CAN_TSR_RQCP0_Pos (0U)
1840#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1841#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1842#define CAN_TSR_TXOK0_Pos (1U)
1843#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1844#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1845#define CAN_TSR_ALST0_Pos (2U)
1846#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1847#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1848#define CAN_TSR_TERR0_Pos (3U)
1849#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1850#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1851#define CAN_TSR_ABRQ0_Pos (7U)
1852#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1853#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1854#define CAN_TSR_RQCP1_Pos (8U)
1855#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1856#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1857#define CAN_TSR_TXOK1_Pos (9U)
1858#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1859#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1860#define CAN_TSR_ALST1_Pos (10U)
1861#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1862#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1863#define CAN_TSR_TERR1_Pos (11U)
1864#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1865#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1866#define CAN_TSR_ABRQ1_Pos (15U)
1867#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1868#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1869#define CAN_TSR_RQCP2_Pos (16U)
1870#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1871#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1872#define CAN_TSR_TXOK2_Pos (17U)
1873#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1874#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1875#define CAN_TSR_ALST2_Pos (18U)
1876#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1877#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1878#define CAN_TSR_TERR2_Pos (19U)
1879#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1880#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1881#define CAN_TSR_ABRQ2_Pos (23U)
1882#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1883#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1884#define CAN_TSR_CODE_Pos (24U)
1885#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1886#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1887
1888#define CAN_TSR_TME_Pos (26U)
1889#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1890#define CAN_TSR_TME CAN_TSR_TME_Msk
1891#define CAN_TSR_TME0_Pos (26U)
1892#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1893#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1894#define CAN_TSR_TME1_Pos (27U)
1895#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1896#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1897#define CAN_TSR_TME2_Pos (28U)
1898#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1899#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1900
1901#define CAN_TSR_LOW_Pos (29U)
1902#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1903#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1904#define CAN_TSR_LOW0_Pos (29U)
1905#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1906#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1907#define CAN_TSR_LOW1_Pos (30U)
1908#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1909#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1910#define CAN_TSR_LOW2_Pos (31U)
1911#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1912#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1913
1914/******************* Bit definition for CAN_RF0R register *******************/
1915#define CAN_RF0R_FMP0_Pos (0U)
1916#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1917#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1918#define CAN_RF0R_FULL0_Pos (3U)
1919#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1920#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1921#define CAN_RF0R_FOVR0_Pos (4U)
1922#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1923#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1924#define CAN_RF0R_RFOM0_Pos (5U)
1925#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1926#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1927
1928/******************* Bit definition for CAN_RF1R register *******************/
1929#define CAN_RF1R_FMP1_Pos (0U)
1930#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1931#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1932#define CAN_RF1R_FULL1_Pos (3U)
1933#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1934#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1935#define CAN_RF1R_FOVR1_Pos (4U)
1936#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1937#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1938#define CAN_RF1R_RFOM1_Pos (5U)
1939#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1940#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1941
1942/******************** Bit definition for CAN_IER register *******************/
1943#define CAN_IER_TMEIE_Pos (0U)
1944#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1945#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1946#define CAN_IER_FMPIE0_Pos (1U)
1947#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1948#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1949#define CAN_IER_FFIE0_Pos (2U)
1950#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1951#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1952#define CAN_IER_FOVIE0_Pos (3U)
1953#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1954#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1955#define CAN_IER_FMPIE1_Pos (4U)
1956#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1957#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1958#define CAN_IER_FFIE1_Pos (5U)
1959#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1960#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1961#define CAN_IER_FOVIE1_Pos (6U)
1962#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1963#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1964#define CAN_IER_EWGIE_Pos (8U)
1965#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1966#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1967#define CAN_IER_EPVIE_Pos (9U)
1968#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1969#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1970#define CAN_IER_BOFIE_Pos (10U)
1971#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1972#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1973#define CAN_IER_LECIE_Pos (11U)
1974#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1975#define CAN_IER_LECIE CAN_IER_LECIE_Msk
1976#define CAN_IER_ERRIE_Pos (15U)
1977#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1978#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1979#define CAN_IER_WKUIE_Pos (16U)
1980#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1981#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1982#define CAN_IER_SLKIE_Pos (17U)
1983#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1984#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1985#define CAN_IER_EWGIE_Pos (8U)
1986
1987/******************** Bit definition for CAN_ESR register *******************/
1988#define CAN_ESR_EWGF_Pos (0U)
1989#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1990#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1991#define CAN_ESR_EPVF_Pos (1U)
1992#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1993#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1994#define CAN_ESR_BOFF_Pos (2U)
1995#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1996#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1997
1998#define CAN_ESR_LEC_Pos (4U)
1999#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2000#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2001#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2002#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2003#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2004
2005#define CAN_ESR_TEC_Pos (16U)
2006#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2007#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2008#define CAN_ESR_REC_Pos (24U)
2009#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2010#define CAN_ESR_REC CAN_ESR_REC_Msk
2011
2012/******************* Bit definition for CAN_BTR register ********************/
2013#define CAN_BTR_BRP_Pos (0U)
2014#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2015#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2016#define CAN_BTR_TS1_Pos (16U)
2017#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2018#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2019#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2020#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2021#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2022#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2023#define CAN_BTR_TS2_Pos (20U)
2024#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2025#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2026#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2027#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2028#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2029#define CAN_BTR_SJW_Pos (24U)
2030#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2031#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2032#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2033#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2034#define CAN_BTR_LBKM_Pos (30U)
2035#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2036#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2037#define CAN_BTR_SILM_Pos (31U)
2038#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2039#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2040
2041
2043/****************** Bit definition for CAN_TI0R register ********************/
2044#define CAN_TI0R_TXRQ_Pos (0U)
2045#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2046#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2047#define CAN_TI0R_RTR_Pos (1U)
2048#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2049#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2050#define CAN_TI0R_IDE_Pos (2U)
2051#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2052#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2053#define CAN_TI0R_EXID_Pos (3U)
2054#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2055#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2056#define CAN_TI0R_STID_Pos (21U)
2057#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2058#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2059
2060/****************** Bit definition for CAN_TDT0R register *******************/
2061#define CAN_TDT0R_DLC_Pos (0U)
2062#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2063#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2064#define CAN_TDT0R_TGT_Pos (8U)
2065#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2066#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2067#define CAN_TDT0R_TIME_Pos (16U)
2068#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2069#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2070
2071/****************** Bit definition for CAN_TDL0R register *******************/
2072#define CAN_TDL0R_DATA0_Pos (0U)
2073#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2074#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2075#define CAN_TDL0R_DATA1_Pos (8U)
2076#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2077#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2078#define CAN_TDL0R_DATA2_Pos (16U)
2079#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2080#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2081#define CAN_TDL0R_DATA3_Pos (24U)
2082#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2083#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2084
2085/****************** Bit definition for CAN_TDH0R register *******************/
2086#define CAN_TDH0R_DATA4_Pos (0U)
2087#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2088#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2089#define CAN_TDH0R_DATA5_Pos (8U)
2090#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2091#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2092#define CAN_TDH0R_DATA6_Pos (16U)
2093#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2094#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2095#define CAN_TDH0R_DATA7_Pos (24U)
2096#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2097#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2098
2099/******************* Bit definition for CAN_TI1R register *******************/
2100#define CAN_TI1R_TXRQ_Pos (0U)
2101#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2102#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2103#define CAN_TI1R_RTR_Pos (1U)
2104#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2105#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2106#define CAN_TI1R_IDE_Pos (2U)
2107#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2108#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2109#define CAN_TI1R_EXID_Pos (3U)
2110#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2111#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2112#define CAN_TI1R_STID_Pos (21U)
2113#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2114#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2115
2116/******************* Bit definition for CAN_TDT1R register ******************/
2117#define CAN_TDT1R_DLC_Pos (0U)
2118#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2119#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2120#define CAN_TDT1R_TGT_Pos (8U)
2121#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2122#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2123#define CAN_TDT1R_TIME_Pos (16U)
2124#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2125#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2126
2127/******************* Bit definition for CAN_TDL1R register ******************/
2128#define CAN_TDL1R_DATA0_Pos (0U)
2129#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2130#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2131#define CAN_TDL1R_DATA1_Pos (8U)
2132#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2133#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2134#define CAN_TDL1R_DATA2_Pos (16U)
2135#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2136#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2137#define CAN_TDL1R_DATA3_Pos (24U)
2138#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2139#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2140
2141/******************* Bit definition for CAN_TDH1R register ******************/
2142#define CAN_TDH1R_DATA4_Pos (0U)
2143#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2144#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2145#define CAN_TDH1R_DATA5_Pos (8U)
2146#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2147#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2148#define CAN_TDH1R_DATA6_Pos (16U)
2149#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2150#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2151#define CAN_TDH1R_DATA7_Pos (24U)
2152#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2153#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2154
2155/******************* Bit definition for CAN_TI2R register *******************/
2156#define CAN_TI2R_TXRQ_Pos (0U)
2157#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2158#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2159#define CAN_TI2R_RTR_Pos (1U)
2160#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2161#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2162#define CAN_TI2R_IDE_Pos (2U)
2163#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2164#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2165#define CAN_TI2R_EXID_Pos (3U)
2166#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2167#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2168#define CAN_TI2R_STID_Pos (21U)
2169#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2170#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2171
2172/******************* Bit definition for CAN_TDT2R register ******************/
2173#define CAN_TDT2R_DLC_Pos (0U)
2174#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2175#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2176#define CAN_TDT2R_TGT_Pos (8U)
2177#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2178#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2179#define CAN_TDT2R_TIME_Pos (16U)
2180#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2181#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2182
2183/******************* Bit definition for CAN_TDL2R register ******************/
2184#define CAN_TDL2R_DATA0_Pos (0U)
2185#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2186#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2187#define CAN_TDL2R_DATA1_Pos (8U)
2188#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2189#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2190#define CAN_TDL2R_DATA2_Pos (16U)
2191#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2192#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2193#define CAN_TDL2R_DATA3_Pos (24U)
2194#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2195#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2196
2197/******************* Bit definition for CAN_TDH2R register ******************/
2198#define CAN_TDH2R_DATA4_Pos (0U)
2199#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2200#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2201#define CAN_TDH2R_DATA5_Pos (8U)
2202#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2203#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2204#define CAN_TDH2R_DATA6_Pos (16U)
2205#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2206#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2207#define CAN_TDH2R_DATA7_Pos (24U)
2208#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2209#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2210
2211/******************* Bit definition for CAN_RI0R register *******************/
2212#define CAN_RI0R_RTR_Pos (1U)
2213#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2214#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2215#define CAN_RI0R_IDE_Pos (2U)
2216#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2217#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2218#define CAN_RI0R_EXID_Pos (3U)
2219#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2220#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2221#define CAN_RI0R_STID_Pos (21U)
2222#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2223#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2224
2225/******************* Bit definition for CAN_RDT0R register ******************/
2226#define CAN_RDT0R_DLC_Pos (0U)
2227#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2228#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2229#define CAN_RDT0R_FMI_Pos (8U)
2230#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2231#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2232#define CAN_RDT0R_TIME_Pos (16U)
2233#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2234#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2235
2236/******************* Bit definition for CAN_RDL0R register ******************/
2237#define CAN_RDL0R_DATA0_Pos (0U)
2238#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2239#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2240#define CAN_RDL0R_DATA1_Pos (8U)
2241#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2242#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2243#define CAN_RDL0R_DATA2_Pos (16U)
2244#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2245#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2246#define CAN_RDL0R_DATA3_Pos (24U)
2247#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2248#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2249
2250/******************* Bit definition for CAN_RDH0R register ******************/
2251#define CAN_RDH0R_DATA4_Pos (0U)
2252#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2253#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2254#define CAN_RDH0R_DATA5_Pos (8U)
2255#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2256#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2257#define CAN_RDH0R_DATA6_Pos (16U)
2258#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2259#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2260#define CAN_RDH0R_DATA7_Pos (24U)
2261#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2262#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2263
2264/******************* Bit definition for CAN_RI1R register *******************/
2265#define CAN_RI1R_RTR_Pos (1U)
2266#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2267#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2268#define CAN_RI1R_IDE_Pos (2U)
2269#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2270#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2271#define CAN_RI1R_EXID_Pos (3U)
2272#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2273#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2274#define CAN_RI1R_STID_Pos (21U)
2275#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2276#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2277
2278/******************* Bit definition for CAN_RDT1R register ******************/
2279#define CAN_RDT1R_DLC_Pos (0U)
2280#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2281#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2282#define CAN_RDT1R_FMI_Pos (8U)
2283#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2284#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2285#define CAN_RDT1R_TIME_Pos (16U)
2286#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2287#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2288
2289/******************* Bit definition for CAN_RDL1R register ******************/
2290#define CAN_RDL1R_DATA0_Pos (0U)
2291#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2292#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2293#define CAN_RDL1R_DATA1_Pos (8U)
2294#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2295#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2296#define CAN_RDL1R_DATA2_Pos (16U)
2297#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2298#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2299#define CAN_RDL1R_DATA3_Pos (24U)
2300#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2301#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2302
2303/******************* Bit definition for CAN_RDH1R register ******************/
2304#define CAN_RDH1R_DATA4_Pos (0U)
2305#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2306#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2307#define CAN_RDH1R_DATA5_Pos (8U)
2308#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2309#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2310#define CAN_RDH1R_DATA6_Pos (16U)
2311#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2312#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2313#define CAN_RDH1R_DATA7_Pos (24U)
2314#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2315#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2316
2318/******************* Bit definition for CAN_FMR register ********************/
2319#define CAN_FMR_FINIT_Pos (0U)
2320#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2321#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2322#define CAN_FMR_CAN2SB_Pos (8U)
2323#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2324#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2325
2326/******************* Bit definition for CAN_FM1R register *******************/
2327#define CAN_FM1R_FBM_Pos (0U)
2328#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2329#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2330#define CAN_FM1R_FBM0_Pos (0U)
2331#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2332#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2333#define CAN_FM1R_FBM1_Pos (1U)
2334#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2335#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2336#define CAN_FM1R_FBM2_Pos (2U)
2337#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2338#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2339#define CAN_FM1R_FBM3_Pos (3U)
2340#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2341#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2342#define CAN_FM1R_FBM4_Pos (4U)
2343#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2344#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2345#define CAN_FM1R_FBM5_Pos (5U)
2346#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2347#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2348#define CAN_FM1R_FBM6_Pos (6U)
2349#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2350#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2351#define CAN_FM1R_FBM7_Pos (7U)
2352#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2353#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2354#define CAN_FM1R_FBM8_Pos (8U)
2355#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2356#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2357#define CAN_FM1R_FBM9_Pos (9U)
2358#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2359#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2360#define CAN_FM1R_FBM10_Pos (10U)
2361#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2362#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2363#define CAN_FM1R_FBM11_Pos (11U)
2364#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2365#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2366#define CAN_FM1R_FBM12_Pos (12U)
2367#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2368#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2369#define CAN_FM1R_FBM13_Pos (13U)
2370#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2371#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2372#define CAN_FM1R_FBM14_Pos (14U)
2373#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2374#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2375#define CAN_FM1R_FBM15_Pos (15U)
2376#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2377#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2378#define CAN_FM1R_FBM16_Pos (16U)
2379#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2380#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2381#define CAN_FM1R_FBM17_Pos (17U)
2382#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2383#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2384#define CAN_FM1R_FBM18_Pos (18U)
2385#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2386#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2387#define CAN_FM1R_FBM19_Pos (19U)
2388#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2389#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2390#define CAN_FM1R_FBM20_Pos (20U)
2391#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2392#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2393#define CAN_FM1R_FBM21_Pos (21U)
2394#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2395#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2396#define CAN_FM1R_FBM22_Pos (22U)
2397#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2398#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2399#define CAN_FM1R_FBM23_Pos (23U)
2400#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2401#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2402#define CAN_FM1R_FBM24_Pos (24U)
2403#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2404#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2405#define CAN_FM1R_FBM25_Pos (25U)
2406#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2407#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2408#define CAN_FM1R_FBM26_Pos (26U)
2409#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2410#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2411#define CAN_FM1R_FBM27_Pos (27U)
2412#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2413#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2414
2415/******************* Bit definition for CAN_FS1R register *******************/
2416#define CAN_FS1R_FSC_Pos (0U)
2417#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2418#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2419#define CAN_FS1R_FSC0_Pos (0U)
2420#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2421#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2422#define CAN_FS1R_FSC1_Pos (1U)
2423#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2424#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2425#define CAN_FS1R_FSC2_Pos (2U)
2426#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2427#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2428#define CAN_FS1R_FSC3_Pos (3U)
2429#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2430#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2431#define CAN_FS1R_FSC4_Pos (4U)
2432#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2433#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2434#define CAN_FS1R_FSC5_Pos (5U)
2435#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2436#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2437#define CAN_FS1R_FSC6_Pos (6U)
2438#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2439#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2440#define CAN_FS1R_FSC7_Pos (7U)
2441#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2442#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2443#define CAN_FS1R_FSC8_Pos (8U)
2444#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2445#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2446#define CAN_FS1R_FSC9_Pos (9U)
2447#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2448#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2449#define CAN_FS1R_FSC10_Pos (10U)
2450#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2451#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2452#define CAN_FS1R_FSC11_Pos (11U)
2453#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2454#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2455#define CAN_FS1R_FSC12_Pos (12U)
2456#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2457#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2458#define CAN_FS1R_FSC13_Pos (13U)
2459#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2460#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2461#define CAN_FS1R_FSC14_Pos (14U)
2462#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2463#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2464#define CAN_FS1R_FSC15_Pos (15U)
2465#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2466#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2467#define CAN_FS1R_FSC16_Pos (16U)
2468#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2469#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2470#define CAN_FS1R_FSC17_Pos (17U)
2471#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2472#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2473#define CAN_FS1R_FSC18_Pos (18U)
2474#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2475#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2476#define CAN_FS1R_FSC19_Pos (19U)
2477#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2478#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2479#define CAN_FS1R_FSC20_Pos (20U)
2480#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2481#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2482#define CAN_FS1R_FSC21_Pos (21U)
2483#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2484#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2485#define CAN_FS1R_FSC22_Pos (22U)
2486#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2487#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2488#define CAN_FS1R_FSC23_Pos (23U)
2489#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2490#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2491#define CAN_FS1R_FSC24_Pos (24U)
2492#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2493#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2494#define CAN_FS1R_FSC25_Pos (25U)
2495#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2496#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2497#define CAN_FS1R_FSC26_Pos (26U)
2498#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2499#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2500#define CAN_FS1R_FSC27_Pos (27U)
2501#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2502#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2503
2504/****************** Bit definition for CAN_FFA1R register *******************/
2505#define CAN_FFA1R_FFA_Pos (0U)
2506#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2507#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2508#define CAN_FFA1R_FFA0_Pos (0U)
2509#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2510#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2511#define CAN_FFA1R_FFA1_Pos (1U)
2512#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2513#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2514#define CAN_FFA1R_FFA2_Pos (2U)
2515#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2516#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2517#define CAN_FFA1R_FFA3_Pos (3U)
2518#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2519#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2520#define CAN_FFA1R_FFA4_Pos (4U)
2521#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2522#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2523#define CAN_FFA1R_FFA5_Pos (5U)
2524#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2525#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2526#define CAN_FFA1R_FFA6_Pos (6U)
2527#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2528#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2529#define CAN_FFA1R_FFA7_Pos (7U)
2530#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2531#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2532#define CAN_FFA1R_FFA8_Pos (8U)
2533#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2534#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2535#define CAN_FFA1R_FFA9_Pos (9U)
2536#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2537#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2538#define CAN_FFA1R_FFA10_Pos (10U)
2539#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2540#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2541#define CAN_FFA1R_FFA11_Pos (11U)
2542#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2543#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2544#define CAN_FFA1R_FFA12_Pos (12U)
2545#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2546#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2547#define CAN_FFA1R_FFA13_Pos (13U)
2548#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2549#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2550#define CAN_FFA1R_FFA14_Pos (14U)
2551#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2552#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2553#define CAN_FFA1R_FFA15_Pos (15U)
2554#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2555#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2556#define CAN_FFA1R_FFA16_Pos (16U)
2557#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2558#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2559#define CAN_FFA1R_FFA17_Pos (17U)
2560#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2561#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2562#define CAN_FFA1R_FFA18_Pos (18U)
2563#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2564#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2565#define CAN_FFA1R_FFA19_Pos (19U)
2566#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2567#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2568#define CAN_FFA1R_FFA20_Pos (20U)
2569#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2570#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2571#define CAN_FFA1R_FFA21_Pos (21U)
2572#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2573#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2574#define CAN_FFA1R_FFA22_Pos (22U)
2575#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2576#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2577#define CAN_FFA1R_FFA23_Pos (23U)
2578#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2579#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2580#define CAN_FFA1R_FFA24_Pos (24U)
2581#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2582#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2583#define CAN_FFA1R_FFA25_Pos (25U)
2584#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2585#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2586#define CAN_FFA1R_FFA26_Pos (26U)
2587#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2588#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2589#define CAN_FFA1R_FFA27_Pos (27U)
2590#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2591#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2592
2593/******************* Bit definition for CAN_FA1R register *******************/
2594#define CAN_FA1R_FACT_Pos (0U)
2595#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2596#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2597#define CAN_FA1R_FACT0_Pos (0U)
2598#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2599#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2600#define CAN_FA1R_FACT1_Pos (1U)
2601#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2602#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2603#define CAN_FA1R_FACT2_Pos (2U)
2604#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2605#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2606#define CAN_FA1R_FACT3_Pos (3U)
2607#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2608#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2609#define CAN_FA1R_FACT4_Pos (4U)
2610#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2611#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2612#define CAN_FA1R_FACT5_Pos (5U)
2613#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2614#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2615#define CAN_FA1R_FACT6_Pos (6U)
2616#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2617#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2618#define CAN_FA1R_FACT7_Pos (7U)
2619#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2620#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2621#define CAN_FA1R_FACT8_Pos (8U)
2622#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2623#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2624#define CAN_FA1R_FACT9_Pos (9U)
2625#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2626#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2627#define CAN_FA1R_FACT10_Pos (10U)
2628#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2629#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2630#define CAN_FA1R_FACT11_Pos (11U)
2631#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2632#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2633#define CAN_FA1R_FACT12_Pos (12U)
2634#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2635#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2636#define CAN_FA1R_FACT13_Pos (13U)
2637#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2638#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2639#define CAN_FA1R_FACT14_Pos (14U)
2640#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2641#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2642#define CAN_FA1R_FACT15_Pos (15U)
2643#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2644#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2645#define CAN_FA1R_FACT16_Pos (16U)
2646#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2647#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2648#define CAN_FA1R_FACT17_Pos (17U)
2649#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2650#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2651#define CAN_FA1R_FACT18_Pos (18U)
2652#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2653#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2654#define CAN_FA1R_FACT19_Pos (19U)
2655#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2656#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2657#define CAN_FA1R_FACT20_Pos (20U)
2658#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2659#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2660#define CAN_FA1R_FACT21_Pos (21U)
2661#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2662#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2663#define CAN_FA1R_FACT22_Pos (22U)
2664#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2665#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2666#define CAN_FA1R_FACT23_Pos (23U)
2667#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2668#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2669#define CAN_FA1R_FACT24_Pos (24U)
2670#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2671#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2672#define CAN_FA1R_FACT25_Pos (25U)
2673#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2674#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2675#define CAN_FA1R_FACT26_Pos (26U)
2676#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2677#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2678#define CAN_FA1R_FACT27_Pos (27U)
2679#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2680#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2681
2682
2683/******************* Bit definition for CAN_F0R1 register *******************/
2684#define CAN_F0R1_FB0_Pos (0U)
2685#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2686#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2687#define CAN_F0R1_FB1_Pos (1U)
2688#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2689#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2690#define CAN_F0R1_FB2_Pos (2U)
2691#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2692#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2693#define CAN_F0R1_FB3_Pos (3U)
2694#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2695#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2696#define CAN_F0R1_FB4_Pos (4U)
2697#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2698#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2699#define CAN_F0R1_FB5_Pos (5U)
2700#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2701#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2702#define CAN_F0R1_FB6_Pos (6U)
2703#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2704#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2705#define CAN_F0R1_FB7_Pos (7U)
2706#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2707#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2708#define CAN_F0R1_FB8_Pos (8U)
2709#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2710#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2711#define CAN_F0R1_FB9_Pos (9U)
2712#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2713#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2714#define CAN_F0R1_FB10_Pos (10U)
2715#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2716#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2717#define CAN_F0R1_FB11_Pos (11U)
2718#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2719#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2720#define CAN_F0R1_FB12_Pos (12U)
2721#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2722#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2723#define CAN_F0R1_FB13_Pos (13U)
2724#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2725#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2726#define CAN_F0R1_FB14_Pos (14U)
2727#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2728#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2729#define CAN_F0R1_FB15_Pos (15U)
2730#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2731#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2732#define CAN_F0R1_FB16_Pos (16U)
2733#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2734#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2735#define CAN_F0R1_FB17_Pos (17U)
2736#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2737#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2738#define CAN_F0R1_FB18_Pos (18U)
2739#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2740#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2741#define CAN_F0R1_FB19_Pos (19U)
2742#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2743#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2744#define CAN_F0R1_FB20_Pos (20U)
2745#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2746#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2747#define CAN_F0R1_FB21_Pos (21U)
2748#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2749#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2750#define CAN_F0R1_FB22_Pos (22U)
2751#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2752#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2753#define CAN_F0R1_FB23_Pos (23U)
2754#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2755#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2756#define CAN_F0R1_FB24_Pos (24U)
2757#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2758#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2759#define CAN_F0R1_FB25_Pos (25U)
2760#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2761#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2762#define CAN_F0R1_FB26_Pos (26U)
2763#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2764#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2765#define CAN_F0R1_FB27_Pos (27U)
2766#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2767#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2768#define CAN_F0R1_FB28_Pos (28U)
2769#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2770#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2771#define CAN_F0R1_FB29_Pos (29U)
2772#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2773#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2774#define CAN_F0R1_FB30_Pos (30U)
2775#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2776#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2777#define CAN_F0R1_FB31_Pos (31U)
2778#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2779#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2780
2781/******************* Bit definition for CAN_F1R1 register *******************/
2782#define CAN_F1R1_FB0_Pos (0U)
2783#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2784#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2785#define CAN_F1R1_FB1_Pos (1U)
2786#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2787#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2788#define CAN_F1R1_FB2_Pos (2U)
2789#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2790#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2791#define CAN_F1R1_FB3_Pos (3U)
2792#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2793#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2794#define CAN_F1R1_FB4_Pos (4U)
2795#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2796#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2797#define CAN_F1R1_FB5_Pos (5U)
2798#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2799#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2800#define CAN_F1R1_FB6_Pos (6U)
2801#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2802#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2803#define CAN_F1R1_FB7_Pos (7U)
2804#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2805#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2806#define CAN_F1R1_FB8_Pos (8U)
2807#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2808#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2809#define CAN_F1R1_FB9_Pos (9U)
2810#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2811#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2812#define CAN_F1R1_FB10_Pos (10U)
2813#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2814#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2815#define CAN_F1R1_FB11_Pos (11U)
2816#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2817#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2818#define CAN_F1R1_FB12_Pos (12U)
2819#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2820#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2821#define CAN_F1R1_FB13_Pos (13U)
2822#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2823#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2824#define CAN_F1R1_FB14_Pos (14U)
2825#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2826#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2827#define CAN_F1R1_FB15_Pos (15U)
2828#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2829#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2830#define CAN_F1R1_FB16_Pos (16U)
2831#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2832#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2833#define CAN_F1R1_FB17_Pos (17U)
2834#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2835#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2836#define CAN_F1R1_FB18_Pos (18U)
2837#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2838#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2839#define CAN_F1R1_FB19_Pos (19U)
2840#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2841#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2842#define CAN_F1R1_FB20_Pos (20U)
2843#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2844#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2845#define CAN_F1R1_FB21_Pos (21U)
2846#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2847#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2848#define CAN_F1R1_FB22_Pos (22U)
2849#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2850#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2851#define CAN_F1R1_FB23_Pos (23U)
2852#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2853#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2854#define CAN_F1R1_FB24_Pos (24U)
2855#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2856#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2857#define CAN_F1R1_FB25_Pos (25U)
2858#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2859#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2860#define CAN_F1R1_FB26_Pos (26U)
2861#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2862#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2863#define CAN_F1R1_FB27_Pos (27U)
2864#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2865#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2866#define CAN_F1R1_FB28_Pos (28U)
2867#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2868#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2869#define CAN_F1R1_FB29_Pos (29U)
2870#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2871#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2872#define CAN_F1R1_FB30_Pos (30U)
2873#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2874#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2875#define CAN_F1R1_FB31_Pos (31U)
2876#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2877#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2878
2879/******************* Bit definition for CAN_F2R1 register *******************/
2880#define CAN_F2R1_FB0_Pos (0U)
2881#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2882#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2883#define CAN_F2R1_FB1_Pos (1U)
2884#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2885#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2886#define CAN_F2R1_FB2_Pos (2U)
2887#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2888#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2889#define CAN_F2R1_FB3_Pos (3U)
2890#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2891#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2892#define CAN_F2R1_FB4_Pos (4U)
2893#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2894#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2895#define CAN_F2R1_FB5_Pos (5U)
2896#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2897#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2898#define CAN_F2R1_FB6_Pos (6U)
2899#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2900#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2901#define CAN_F2R1_FB7_Pos (7U)
2902#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2903#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2904#define CAN_F2R1_FB8_Pos (8U)
2905#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2906#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2907#define CAN_F2R1_FB9_Pos (9U)
2908#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2909#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2910#define CAN_F2R1_FB10_Pos (10U)
2911#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2912#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2913#define CAN_F2R1_FB11_Pos (11U)
2914#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2915#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2916#define CAN_F2R1_FB12_Pos (12U)
2917#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2918#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2919#define CAN_F2R1_FB13_Pos (13U)
2920#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2921#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2922#define CAN_F2R1_FB14_Pos (14U)
2923#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2924#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2925#define CAN_F2R1_FB15_Pos (15U)
2926#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2927#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2928#define CAN_F2R1_FB16_Pos (16U)
2929#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2930#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2931#define CAN_F2R1_FB17_Pos (17U)
2932#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2933#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2934#define CAN_F2R1_FB18_Pos (18U)
2935#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2936#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2937#define CAN_F2R1_FB19_Pos (19U)
2938#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2939#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2940#define CAN_F2R1_FB20_Pos (20U)
2941#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2942#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2943#define CAN_F2R1_FB21_Pos (21U)
2944#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2945#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2946#define CAN_F2R1_FB22_Pos (22U)
2947#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2948#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2949#define CAN_F2R1_FB23_Pos (23U)
2950#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2951#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2952#define CAN_F2R1_FB24_Pos (24U)
2953#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2954#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2955#define CAN_F2R1_FB25_Pos (25U)
2956#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2957#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2958#define CAN_F2R1_FB26_Pos (26U)
2959#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2960#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2961#define CAN_F2R1_FB27_Pos (27U)
2962#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2963#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2964#define CAN_F2R1_FB28_Pos (28U)
2965#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2966#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2967#define CAN_F2R1_FB29_Pos (29U)
2968#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2969#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2970#define CAN_F2R1_FB30_Pos (30U)
2971#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2972#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2973#define CAN_F2R1_FB31_Pos (31U)
2974#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2975#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2976
2977/******************* Bit definition for CAN_F3R1 register *******************/
2978#define CAN_F3R1_FB0_Pos (0U)
2979#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2980#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2981#define CAN_F3R1_FB1_Pos (1U)
2982#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2983#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2984#define CAN_F3R1_FB2_Pos (2U)
2985#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2986#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2987#define CAN_F3R1_FB3_Pos (3U)
2988#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2989#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2990#define CAN_F3R1_FB4_Pos (4U)
2991#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2992#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2993#define CAN_F3R1_FB5_Pos (5U)
2994#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2995#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2996#define CAN_F3R1_FB6_Pos (6U)
2997#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2998#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2999#define CAN_F3R1_FB7_Pos (7U)
3000#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3001#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3002#define CAN_F3R1_FB8_Pos (8U)
3003#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3004#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3005#define CAN_F3R1_FB9_Pos (9U)
3006#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3007#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3008#define CAN_F3R1_FB10_Pos (10U)
3009#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3010#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3011#define CAN_F3R1_FB11_Pos (11U)
3012#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3013#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3014#define CAN_F3R1_FB12_Pos (12U)
3015#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3016#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3017#define CAN_F3R1_FB13_Pos (13U)
3018#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3019#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3020#define CAN_F3R1_FB14_Pos (14U)
3021#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3022#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3023#define CAN_F3R1_FB15_Pos (15U)
3024#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3025#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3026#define CAN_F3R1_FB16_Pos (16U)
3027#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3028#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3029#define CAN_F3R1_FB17_Pos (17U)
3030#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3031#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3032#define CAN_F3R1_FB18_Pos (18U)
3033#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3034#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3035#define CAN_F3R1_FB19_Pos (19U)
3036#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3037#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3038#define CAN_F3R1_FB20_Pos (20U)
3039#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3040#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3041#define CAN_F3R1_FB21_Pos (21U)
3042#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3043#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3044#define CAN_F3R1_FB22_Pos (22U)
3045#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3046#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3047#define CAN_F3R1_FB23_Pos (23U)
3048#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3049#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3050#define CAN_F3R1_FB24_Pos (24U)
3051#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3052#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3053#define CAN_F3R1_FB25_Pos (25U)
3054#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3055#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3056#define CAN_F3R1_FB26_Pos (26U)
3057#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3058#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3059#define CAN_F3R1_FB27_Pos (27U)
3060#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3061#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3062#define CAN_F3R1_FB28_Pos (28U)
3063#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3064#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3065#define CAN_F3R1_FB29_Pos (29U)
3066#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3067#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3068#define CAN_F3R1_FB30_Pos (30U)
3069#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3070#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3071#define CAN_F3R1_FB31_Pos (31U)
3072#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3073#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3074
3075/******************* Bit definition for CAN_F4R1 register *******************/
3076#define CAN_F4R1_FB0_Pos (0U)
3077#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3078#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3079#define CAN_F4R1_FB1_Pos (1U)
3080#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3081#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3082#define CAN_F4R1_FB2_Pos (2U)
3083#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3084#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3085#define CAN_F4R1_FB3_Pos (3U)
3086#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3087#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3088#define CAN_F4R1_FB4_Pos (4U)
3089#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3090#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3091#define CAN_F4R1_FB5_Pos (5U)
3092#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3093#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3094#define CAN_F4R1_FB6_Pos (6U)
3095#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3096#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3097#define CAN_F4R1_FB7_Pos (7U)
3098#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3099#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3100#define CAN_F4R1_FB8_Pos (8U)
3101#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3102#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3103#define CAN_F4R1_FB9_Pos (9U)
3104#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3105#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3106#define CAN_F4R1_FB10_Pos (10U)
3107#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3108#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3109#define CAN_F4R1_FB11_Pos (11U)
3110#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3111#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3112#define CAN_F4R1_FB12_Pos (12U)
3113#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3114#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3115#define CAN_F4R1_FB13_Pos (13U)
3116#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3117#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3118#define CAN_F4R1_FB14_Pos (14U)
3119#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3120#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3121#define CAN_F4R1_FB15_Pos (15U)
3122#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3123#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3124#define CAN_F4R1_FB16_Pos (16U)
3125#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3126#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3127#define CAN_F4R1_FB17_Pos (17U)
3128#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3129#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3130#define CAN_F4R1_FB18_Pos (18U)
3131#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3132#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3133#define CAN_F4R1_FB19_Pos (19U)
3134#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3135#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3136#define CAN_F4R1_FB20_Pos (20U)
3137#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3138#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3139#define CAN_F4R1_FB21_Pos (21U)
3140#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3141#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3142#define CAN_F4R1_FB22_Pos (22U)
3143#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3144#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3145#define CAN_F4R1_FB23_Pos (23U)
3146#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3147#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3148#define CAN_F4R1_FB24_Pos (24U)
3149#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3150#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3151#define CAN_F4R1_FB25_Pos (25U)
3152#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3153#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3154#define CAN_F4R1_FB26_Pos (26U)
3155#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3156#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3157#define CAN_F4R1_FB27_Pos (27U)
3158#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3159#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3160#define CAN_F4R1_FB28_Pos (28U)
3161#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3162#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3163#define CAN_F4R1_FB29_Pos (29U)
3164#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3165#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3166#define CAN_F4R1_FB30_Pos (30U)
3167#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3168#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3169#define CAN_F4R1_FB31_Pos (31U)
3170#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3171#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3172
3173/******************* Bit definition for CAN_F5R1 register *******************/
3174#define CAN_F5R1_FB0_Pos (0U)
3175#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3176#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3177#define CAN_F5R1_FB1_Pos (1U)
3178#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3179#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3180#define CAN_F5R1_FB2_Pos (2U)
3181#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3182#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3183#define CAN_F5R1_FB3_Pos (3U)
3184#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3185#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3186#define CAN_F5R1_FB4_Pos (4U)
3187#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3188#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3189#define CAN_F5R1_FB5_Pos (5U)
3190#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3191#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3192#define CAN_F5R1_FB6_Pos (6U)
3193#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3194#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3195#define CAN_F5R1_FB7_Pos (7U)
3196#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3197#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3198#define CAN_F5R1_FB8_Pos (8U)
3199#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3200#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3201#define CAN_F5R1_FB9_Pos (9U)
3202#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3203#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3204#define CAN_F5R1_FB10_Pos (10U)
3205#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3206#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3207#define CAN_F5R1_FB11_Pos (11U)
3208#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3209#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3210#define CAN_F5R1_FB12_Pos (12U)
3211#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3212#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3213#define CAN_F5R1_FB13_Pos (13U)
3214#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3215#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3216#define CAN_F5R1_FB14_Pos (14U)
3217#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3218#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3219#define CAN_F5R1_FB15_Pos (15U)
3220#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3221#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3222#define CAN_F5R1_FB16_Pos (16U)
3223#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3224#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3225#define CAN_F5R1_FB17_Pos (17U)
3226#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3227#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3228#define CAN_F5R1_FB18_Pos (18U)
3229#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3230#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3231#define CAN_F5R1_FB19_Pos (19U)
3232#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3233#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3234#define CAN_F5R1_FB20_Pos (20U)
3235#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3236#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3237#define CAN_F5R1_FB21_Pos (21U)
3238#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3239#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3240#define CAN_F5R1_FB22_Pos (22U)
3241#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3242#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3243#define CAN_F5R1_FB23_Pos (23U)
3244#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3245#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3246#define CAN_F5R1_FB24_Pos (24U)
3247#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3248#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3249#define CAN_F5R1_FB25_Pos (25U)
3250#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3251#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3252#define CAN_F5R1_FB26_Pos (26U)
3253#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3254#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3255#define CAN_F5R1_FB27_Pos (27U)
3256#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3257#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3258#define CAN_F5R1_FB28_Pos (28U)
3259#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3260#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3261#define CAN_F5R1_FB29_Pos (29U)
3262#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3263#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3264#define CAN_F5R1_FB30_Pos (30U)
3265#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3266#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3267#define CAN_F5R1_FB31_Pos (31U)
3268#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3269#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3270
3271/******************* Bit definition for CAN_F6R1 register *******************/
3272#define CAN_F6R1_FB0_Pos (0U)
3273#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3274#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3275#define CAN_F6R1_FB1_Pos (1U)
3276#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3277#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3278#define CAN_F6R1_FB2_Pos (2U)
3279#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3280#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3281#define CAN_F6R1_FB3_Pos (3U)
3282#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3283#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3284#define CAN_F6R1_FB4_Pos (4U)
3285#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3286#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3287#define CAN_F6R1_FB5_Pos (5U)
3288#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3289#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3290#define CAN_F6R1_FB6_Pos (6U)
3291#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3292#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3293#define CAN_F6R1_FB7_Pos (7U)
3294#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3295#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3296#define CAN_F6R1_FB8_Pos (8U)
3297#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3298#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3299#define CAN_F6R1_FB9_Pos (9U)
3300#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3301#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3302#define CAN_F6R1_FB10_Pos (10U)
3303#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3304#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3305#define CAN_F6R1_FB11_Pos (11U)
3306#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3307#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3308#define CAN_F6R1_FB12_Pos (12U)
3309#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3310#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3311#define CAN_F6R1_FB13_Pos (13U)
3312#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3313#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3314#define CAN_F6R1_FB14_Pos (14U)
3315#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3316#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3317#define CAN_F6R1_FB15_Pos (15U)
3318#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3319#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3320#define CAN_F6R1_FB16_Pos (16U)
3321#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3322#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3323#define CAN_F6R1_FB17_Pos (17U)
3324#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3325#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3326#define CAN_F6R1_FB18_Pos (18U)
3327#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3328#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3329#define CAN_F6R1_FB19_Pos (19U)
3330#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3331#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3332#define CAN_F6R1_FB20_Pos (20U)
3333#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3334#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3335#define CAN_F6R1_FB21_Pos (21U)
3336#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3337#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3338#define CAN_F6R1_FB22_Pos (22U)
3339#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3340#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3341#define CAN_F6R1_FB23_Pos (23U)
3342#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3343#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3344#define CAN_F6R1_FB24_Pos (24U)
3345#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3346#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3347#define CAN_F6R1_FB25_Pos (25U)
3348#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3349#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3350#define CAN_F6R1_FB26_Pos (26U)
3351#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3352#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3353#define CAN_F6R1_FB27_Pos (27U)
3354#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3355#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3356#define CAN_F6R1_FB28_Pos (28U)
3357#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3358#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3359#define CAN_F6R1_FB29_Pos (29U)
3360#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3361#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3362#define CAN_F6R1_FB30_Pos (30U)
3363#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3364#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3365#define CAN_F6R1_FB31_Pos (31U)
3366#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3367#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3368
3369/******************* Bit definition for CAN_F7R1 register *******************/
3370#define CAN_F7R1_FB0_Pos (0U)
3371#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3372#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3373#define CAN_F7R1_FB1_Pos (1U)
3374#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3375#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3376#define CAN_F7R1_FB2_Pos (2U)
3377#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3378#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3379#define CAN_F7R1_FB3_Pos (3U)
3380#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3381#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3382#define CAN_F7R1_FB4_Pos (4U)
3383#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3384#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3385#define CAN_F7R1_FB5_Pos (5U)
3386#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3387#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3388#define CAN_F7R1_FB6_Pos (6U)
3389#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3390#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3391#define CAN_F7R1_FB7_Pos (7U)
3392#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3393#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3394#define CAN_F7R1_FB8_Pos (8U)
3395#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3396#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3397#define CAN_F7R1_FB9_Pos (9U)
3398#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3399#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3400#define CAN_F7R1_FB10_Pos (10U)
3401#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3402#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3403#define CAN_F7R1_FB11_Pos (11U)
3404#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3405#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3406#define CAN_F7R1_FB12_Pos (12U)
3407#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3408#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3409#define CAN_F7R1_FB13_Pos (13U)
3410#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3411#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3412#define CAN_F7R1_FB14_Pos (14U)
3413#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3414#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3415#define CAN_F7R1_FB15_Pos (15U)
3416#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3417#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3418#define CAN_F7R1_FB16_Pos (16U)
3419#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3420#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3421#define CAN_F7R1_FB17_Pos (17U)
3422#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3423#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3424#define CAN_F7R1_FB18_Pos (18U)
3425#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3426#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3427#define CAN_F7R1_FB19_Pos (19U)
3428#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3429#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3430#define CAN_F7R1_FB20_Pos (20U)
3431#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3432#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3433#define CAN_F7R1_FB21_Pos (21U)
3434#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3435#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3436#define CAN_F7R1_FB22_Pos (22U)
3437#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3438#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3439#define CAN_F7R1_FB23_Pos (23U)
3440#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3441#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3442#define CAN_F7R1_FB24_Pos (24U)
3443#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3444#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3445#define CAN_F7R1_FB25_Pos (25U)
3446#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3447#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3448#define CAN_F7R1_FB26_Pos (26U)
3449#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3450#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3451#define CAN_F7R1_FB27_Pos (27U)
3452#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3453#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3454#define CAN_F7R1_FB28_Pos (28U)
3455#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3456#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3457#define CAN_F7R1_FB29_Pos (29U)
3458#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3459#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3460#define CAN_F7R1_FB30_Pos (30U)
3461#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3462#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3463#define CAN_F7R1_FB31_Pos (31U)
3464#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3465#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3466
3467/******************* Bit definition for CAN_F8R1 register *******************/
3468#define CAN_F8R1_FB0_Pos (0U)
3469#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3470#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3471#define CAN_F8R1_FB1_Pos (1U)
3472#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3473#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3474#define CAN_F8R1_FB2_Pos (2U)
3475#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3476#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3477#define CAN_F8R1_FB3_Pos (3U)
3478#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3479#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3480#define CAN_F8R1_FB4_Pos (4U)
3481#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3482#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3483#define CAN_F8R1_FB5_Pos (5U)
3484#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3485#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3486#define CAN_F8R1_FB6_Pos (6U)
3487#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3488#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3489#define CAN_F8R1_FB7_Pos (7U)
3490#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3491#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3492#define CAN_F8R1_FB8_Pos (8U)
3493#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3494#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3495#define CAN_F8R1_FB9_Pos (9U)
3496#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3497#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3498#define CAN_F8R1_FB10_Pos (10U)
3499#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3500#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3501#define CAN_F8R1_FB11_Pos (11U)
3502#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3503#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3504#define CAN_F8R1_FB12_Pos (12U)
3505#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3506#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3507#define CAN_F8R1_FB13_Pos (13U)
3508#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3509#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3510#define CAN_F8R1_FB14_Pos (14U)
3511#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3512#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3513#define CAN_F8R1_FB15_Pos (15U)
3514#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3515#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3516#define CAN_F8R1_FB16_Pos (16U)
3517#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3518#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3519#define CAN_F8R1_FB17_Pos (17U)
3520#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3521#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3522#define CAN_F8R1_FB18_Pos (18U)
3523#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3524#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3525#define CAN_F8R1_FB19_Pos (19U)
3526#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3527#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3528#define CAN_F8R1_FB20_Pos (20U)
3529#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3530#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3531#define CAN_F8R1_FB21_Pos (21U)
3532#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3533#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3534#define CAN_F8R1_FB22_Pos (22U)
3535#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3536#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3537#define CAN_F8R1_FB23_Pos (23U)
3538#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3539#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3540#define CAN_F8R1_FB24_Pos (24U)
3541#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3542#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3543#define CAN_F8R1_FB25_Pos (25U)
3544#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3545#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3546#define CAN_F8R1_FB26_Pos (26U)
3547#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3548#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3549#define CAN_F8R1_FB27_Pos (27U)
3550#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3551#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3552#define CAN_F8R1_FB28_Pos (28U)
3553#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3554#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3555#define CAN_F8R1_FB29_Pos (29U)
3556#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3557#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3558#define CAN_F8R1_FB30_Pos (30U)
3559#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3560#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3561#define CAN_F8R1_FB31_Pos (31U)
3562#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3563#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3564
3565/******************* Bit definition for CAN_F9R1 register *******************/
3566#define CAN_F9R1_FB0_Pos (0U)
3567#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3568#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3569#define CAN_F9R1_FB1_Pos (1U)
3570#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3571#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3572#define CAN_F9R1_FB2_Pos (2U)
3573#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3574#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3575#define CAN_F9R1_FB3_Pos (3U)
3576#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3577#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3578#define CAN_F9R1_FB4_Pos (4U)
3579#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3580#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3581#define CAN_F9R1_FB5_Pos (5U)
3582#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3583#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3584#define CAN_F9R1_FB6_Pos (6U)
3585#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3586#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3587#define CAN_F9R1_FB7_Pos (7U)
3588#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3589#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3590#define CAN_F9R1_FB8_Pos (8U)
3591#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3592#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3593#define CAN_F9R1_FB9_Pos (9U)
3594#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3595#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3596#define CAN_F9R1_FB10_Pos (10U)
3597#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3598#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3599#define CAN_F9R1_FB11_Pos (11U)
3600#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3601#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3602#define CAN_F9R1_FB12_Pos (12U)
3603#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3604#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3605#define CAN_F9R1_FB13_Pos (13U)
3606#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3607#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3608#define CAN_F9R1_FB14_Pos (14U)
3609#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3610#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3611#define CAN_F9R1_FB15_Pos (15U)
3612#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3613#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3614#define CAN_F9R1_FB16_Pos (16U)
3615#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3616#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3617#define CAN_F9R1_FB17_Pos (17U)
3618#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3619#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3620#define CAN_F9R1_FB18_Pos (18U)
3621#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3622#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3623#define CAN_F9R1_FB19_Pos (19U)
3624#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3625#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3626#define CAN_F9R1_FB20_Pos (20U)
3627#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3628#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3629#define CAN_F9R1_FB21_Pos (21U)
3630#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3631#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3632#define CAN_F9R1_FB22_Pos (22U)
3633#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3634#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3635#define CAN_F9R1_FB23_Pos (23U)
3636#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3637#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3638#define CAN_F9R1_FB24_Pos (24U)
3639#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3640#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3641#define CAN_F9R1_FB25_Pos (25U)
3642#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3643#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3644#define CAN_F9R1_FB26_Pos (26U)
3645#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3646#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3647#define CAN_F9R1_FB27_Pos (27U)
3648#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3649#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3650#define CAN_F9R1_FB28_Pos (28U)
3651#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3652#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3653#define CAN_F9R1_FB29_Pos (29U)
3654#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3655#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3656#define CAN_F9R1_FB30_Pos (30U)
3657#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3658#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3659#define CAN_F9R1_FB31_Pos (31U)
3660#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3661#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3662
3663/******************* Bit definition for CAN_F10R1 register ******************/
3664#define CAN_F10R1_FB0_Pos (0U)
3665#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3666#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3667#define CAN_F10R1_FB1_Pos (1U)
3668#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3669#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3670#define CAN_F10R1_FB2_Pos (2U)
3671#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3672#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3673#define CAN_F10R1_FB3_Pos (3U)
3674#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3675#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3676#define CAN_F10R1_FB4_Pos (4U)
3677#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3678#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3679#define CAN_F10R1_FB5_Pos (5U)
3680#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3681#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3682#define CAN_F10R1_FB6_Pos (6U)
3683#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3684#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3685#define CAN_F10R1_FB7_Pos (7U)
3686#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3687#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3688#define CAN_F10R1_FB8_Pos (8U)
3689#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3690#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3691#define CAN_F10R1_FB9_Pos (9U)
3692#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3693#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3694#define CAN_F10R1_FB10_Pos (10U)
3695#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3696#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3697#define CAN_F10R1_FB11_Pos (11U)
3698#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3699#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3700#define CAN_F10R1_FB12_Pos (12U)
3701#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3702#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3703#define CAN_F10R1_FB13_Pos (13U)
3704#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3705#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3706#define CAN_F10R1_FB14_Pos (14U)
3707#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3708#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3709#define CAN_F10R1_FB15_Pos (15U)
3710#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3711#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3712#define CAN_F10R1_FB16_Pos (16U)
3713#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3714#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3715#define CAN_F10R1_FB17_Pos (17U)
3716#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3717#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3718#define CAN_F10R1_FB18_Pos (18U)
3719#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3720#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3721#define CAN_F10R1_FB19_Pos (19U)
3722#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3723#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3724#define CAN_F10R1_FB20_Pos (20U)
3725#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3726#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3727#define CAN_F10R1_FB21_Pos (21U)
3728#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3729#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3730#define CAN_F10R1_FB22_Pos (22U)
3731#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3732#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3733#define CAN_F10R1_FB23_Pos (23U)
3734#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3735#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3736#define CAN_F10R1_FB24_Pos (24U)
3737#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3738#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3739#define CAN_F10R1_FB25_Pos (25U)
3740#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3741#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3742#define CAN_F10R1_FB26_Pos (26U)
3743#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3744#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3745#define CAN_F10R1_FB27_Pos (27U)
3746#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3747#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3748#define CAN_F10R1_FB28_Pos (28U)
3749#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3750#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3751#define CAN_F10R1_FB29_Pos (29U)
3752#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3753#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3754#define CAN_F10R1_FB30_Pos (30U)
3755#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3756#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3757#define CAN_F10R1_FB31_Pos (31U)
3758#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3759#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3760
3761/******************* Bit definition for CAN_F11R1 register ******************/
3762#define CAN_F11R1_FB0_Pos (0U)
3763#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3764#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3765#define CAN_F11R1_FB1_Pos (1U)
3766#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3767#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3768#define CAN_F11R1_FB2_Pos (2U)
3769#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3770#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3771#define CAN_F11R1_FB3_Pos (3U)
3772#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3773#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3774#define CAN_F11R1_FB4_Pos (4U)
3775#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3776#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3777#define CAN_F11R1_FB5_Pos (5U)
3778#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3779#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3780#define CAN_F11R1_FB6_Pos (6U)
3781#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3782#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3783#define CAN_F11R1_FB7_Pos (7U)
3784#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3785#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3786#define CAN_F11R1_FB8_Pos (8U)
3787#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3788#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3789#define CAN_F11R1_FB9_Pos (9U)
3790#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3791#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3792#define CAN_F11R1_FB10_Pos (10U)
3793#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3794#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3795#define CAN_F11R1_FB11_Pos (11U)
3796#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3797#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3798#define CAN_F11R1_FB12_Pos (12U)
3799#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3800#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3801#define CAN_F11R1_FB13_Pos (13U)
3802#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3803#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3804#define CAN_F11R1_FB14_Pos (14U)
3805#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3806#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3807#define CAN_F11R1_FB15_Pos (15U)
3808#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3809#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3810#define CAN_F11R1_FB16_Pos (16U)
3811#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3812#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3813#define CAN_F11R1_FB17_Pos (17U)
3814#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3815#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3816#define CAN_F11R1_FB18_Pos (18U)
3817#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3818#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3819#define CAN_F11R1_FB19_Pos (19U)
3820#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3821#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3822#define CAN_F11R1_FB20_Pos (20U)
3823#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3824#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3825#define CAN_F11R1_FB21_Pos (21U)
3826#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3827#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3828#define CAN_F11R1_FB22_Pos (22U)
3829#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3830#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3831#define CAN_F11R1_FB23_Pos (23U)
3832#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3833#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3834#define CAN_F11R1_FB24_Pos (24U)
3835#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3836#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3837#define CAN_F11R1_FB25_Pos (25U)
3838#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3839#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3840#define CAN_F11R1_FB26_Pos (26U)
3841#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3842#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3843#define CAN_F11R1_FB27_Pos (27U)
3844#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3845#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3846#define CAN_F11R1_FB28_Pos (28U)
3847#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3848#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3849#define CAN_F11R1_FB29_Pos (29U)
3850#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3851#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3852#define CAN_F11R1_FB30_Pos (30U)
3853#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3854#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3855#define CAN_F11R1_FB31_Pos (31U)
3856#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3857#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3858
3859/******************* Bit definition for CAN_F12R1 register ******************/
3860#define CAN_F12R1_FB0_Pos (0U)
3861#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3862#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3863#define CAN_F12R1_FB1_Pos (1U)
3864#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3865#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3866#define CAN_F12R1_FB2_Pos (2U)
3867#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3868#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3869#define CAN_F12R1_FB3_Pos (3U)
3870#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3871#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3872#define CAN_F12R1_FB4_Pos (4U)
3873#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3874#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3875#define CAN_F12R1_FB5_Pos (5U)
3876#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3877#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3878#define CAN_F12R1_FB6_Pos (6U)
3879#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3880#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3881#define CAN_F12R1_FB7_Pos (7U)
3882#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3883#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3884#define CAN_F12R1_FB8_Pos (8U)
3885#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3886#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3887#define CAN_F12R1_FB9_Pos (9U)
3888#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3889#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3890#define CAN_F12R1_FB10_Pos (10U)
3891#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3892#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3893#define CAN_F12R1_FB11_Pos (11U)
3894#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3895#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3896#define CAN_F12R1_FB12_Pos (12U)
3897#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3898#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3899#define CAN_F12R1_FB13_Pos (13U)
3900#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3901#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3902#define CAN_F12R1_FB14_Pos (14U)
3903#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3904#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3905#define CAN_F12R1_FB15_Pos (15U)
3906#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3907#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3908#define CAN_F12R1_FB16_Pos (16U)
3909#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3910#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3911#define CAN_F12R1_FB17_Pos (17U)
3912#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3913#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3914#define CAN_F12R1_FB18_Pos (18U)
3915#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3916#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3917#define CAN_F12R1_FB19_Pos (19U)
3918#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3919#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3920#define CAN_F12R1_FB20_Pos (20U)
3921#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3922#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3923#define CAN_F12R1_FB21_Pos (21U)
3924#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3925#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3926#define CAN_F12R1_FB22_Pos (22U)
3927#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3928#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3929#define CAN_F12R1_FB23_Pos (23U)
3930#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3931#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3932#define CAN_F12R1_FB24_Pos (24U)
3933#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3934#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3935#define CAN_F12R1_FB25_Pos (25U)
3936#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3937#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3938#define CAN_F12R1_FB26_Pos (26U)
3939#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3940#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3941#define CAN_F12R1_FB27_Pos (27U)
3942#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3943#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3944#define CAN_F12R1_FB28_Pos (28U)
3945#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3946#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3947#define CAN_F12R1_FB29_Pos (29U)
3948#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3949#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3950#define CAN_F12R1_FB30_Pos (30U)
3951#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3952#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3953#define CAN_F12R1_FB31_Pos (31U)
3954#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3955#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3956
3957/******************* Bit definition for CAN_F13R1 register ******************/
3958#define CAN_F13R1_FB0_Pos (0U)
3959#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3960#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3961#define CAN_F13R1_FB1_Pos (1U)
3962#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3963#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3964#define CAN_F13R1_FB2_Pos (2U)
3965#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3966#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3967#define CAN_F13R1_FB3_Pos (3U)
3968#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3969#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3970#define CAN_F13R1_FB4_Pos (4U)
3971#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3972#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3973#define CAN_F13R1_FB5_Pos (5U)
3974#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3975#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3976#define CAN_F13R1_FB6_Pos (6U)
3977#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3978#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3979#define CAN_F13R1_FB7_Pos (7U)
3980#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3981#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3982#define CAN_F13R1_FB8_Pos (8U)
3983#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3984#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3985#define CAN_F13R1_FB9_Pos (9U)
3986#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3987#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3988#define CAN_F13R1_FB10_Pos (10U)
3989#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3990#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3991#define CAN_F13R1_FB11_Pos (11U)
3992#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3993#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3994#define CAN_F13R1_FB12_Pos (12U)
3995#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3996#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3997#define CAN_F13R1_FB13_Pos (13U)
3998#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3999#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4000#define CAN_F13R1_FB14_Pos (14U)
4001#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4002#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4003#define CAN_F13R1_FB15_Pos (15U)
4004#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4005#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4006#define CAN_F13R1_FB16_Pos (16U)
4007#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4008#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4009#define CAN_F13R1_FB17_Pos (17U)
4010#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4011#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4012#define CAN_F13R1_FB18_Pos (18U)
4013#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4014#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4015#define CAN_F13R1_FB19_Pos (19U)
4016#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4017#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4018#define CAN_F13R1_FB20_Pos (20U)
4019#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4020#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4021#define CAN_F13R1_FB21_Pos (21U)
4022#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4023#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4024#define CAN_F13R1_FB22_Pos (22U)
4025#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4026#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4027#define CAN_F13R1_FB23_Pos (23U)
4028#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4029#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4030#define CAN_F13R1_FB24_Pos (24U)
4031#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4032#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4033#define CAN_F13R1_FB25_Pos (25U)
4034#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4035#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4036#define CAN_F13R1_FB26_Pos (26U)
4037#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4038#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4039#define CAN_F13R1_FB27_Pos (27U)
4040#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4041#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4042#define CAN_F13R1_FB28_Pos (28U)
4043#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4044#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4045#define CAN_F13R1_FB29_Pos (29U)
4046#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4047#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4048#define CAN_F13R1_FB30_Pos (30U)
4049#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4050#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4051#define CAN_F13R1_FB31_Pos (31U)
4052#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4053#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4054
4055/******************* Bit definition for CAN_F0R2 register *******************/
4056#define CAN_F0R2_FB0_Pos (0U)
4057#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4058#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4059#define CAN_F0R2_FB1_Pos (1U)
4060#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4061#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4062#define CAN_F0R2_FB2_Pos (2U)
4063#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4064#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4065#define CAN_F0R2_FB3_Pos (3U)
4066#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4067#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4068#define CAN_F0R2_FB4_Pos (4U)
4069#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4070#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4071#define CAN_F0R2_FB5_Pos (5U)
4072#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4073#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4074#define CAN_F0R2_FB6_Pos (6U)
4075#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4076#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4077#define CAN_F0R2_FB7_Pos (7U)
4078#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4079#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4080#define CAN_F0R2_FB8_Pos (8U)
4081#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4082#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4083#define CAN_F0R2_FB9_Pos (9U)
4084#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4085#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4086#define CAN_F0R2_FB10_Pos (10U)
4087#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4088#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4089#define CAN_F0R2_FB11_Pos (11U)
4090#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4091#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4092#define CAN_F0R2_FB12_Pos (12U)
4093#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4094#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4095#define CAN_F0R2_FB13_Pos (13U)
4096#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4097#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4098#define CAN_F0R2_FB14_Pos (14U)
4099#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4100#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4101#define CAN_F0R2_FB15_Pos (15U)
4102#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4103#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4104#define CAN_F0R2_FB16_Pos (16U)
4105#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4106#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4107#define CAN_F0R2_FB17_Pos (17U)
4108#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4109#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4110#define CAN_F0R2_FB18_Pos (18U)
4111#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4112#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4113#define CAN_F0R2_FB19_Pos (19U)
4114#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4115#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4116#define CAN_F0R2_FB20_Pos (20U)
4117#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4118#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4119#define CAN_F0R2_FB21_Pos (21U)
4120#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4121#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4122#define CAN_F0R2_FB22_Pos (22U)
4123#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4124#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4125#define CAN_F0R2_FB23_Pos (23U)
4126#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4127#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4128#define CAN_F0R2_FB24_Pos (24U)
4129#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4130#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4131#define CAN_F0R2_FB25_Pos (25U)
4132#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4133#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4134#define CAN_F0R2_FB26_Pos (26U)
4135#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4136#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4137#define CAN_F0R2_FB27_Pos (27U)
4138#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4139#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4140#define CAN_F0R2_FB28_Pos (28U)
4141#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4142#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4143#define CAN_F0R2_FB29_Pos (29U)
4144#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4145#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4146#define CAN_F0R2_FB30_Pos (30U)
4147#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4148#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4149#define CAN_F0R2_FB31_Pos (31U)
4150#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4151#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4152
4153/******************* Bit definition for CAN_F1R2 register *******************/
4154#define CAN_F1R2_FB0_Pos (0U)
4155#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4156#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4157#define CAN_F1R2_FB1_Pos (1U)
4158#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4159#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4160#define CAN_F1R2_FB2_Pos (2U)
4161#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4162#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4163#define CAN_F1R2_FB3_Pos (3U)
4164#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4165#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4166#define CAN_F1R2_FB4_Pos (4U)
4167#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4168#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4169#define CAN_F1R2_FB5_Pos (5U)
4170#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4171#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4172#define CAN_F1R2_FB6_Pos (6U)
4173#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4174#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4175#define CAN_F1R2_FB7_Pos (7U)
4176#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4177#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4178#define CAN_F1R2_FB8_Pos (8U)
4179#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4180#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4181#define CAN_F1R2_FB9_Pos (9U)
4182#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4183#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4184#define CAN_F1R2_FB10_Pos (10U)
4185#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4186#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4187#define CAN_F1R2_FB11_Pos (11U)
4188#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4189#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4190#define CAN_F1R2_FB12_Pos (12U)
4191#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4192#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4193#define CAN_F1R2_FB13_Pos (13U)
4194#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4195#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4196#define CAN_F1R2_FB14_Pos (14U)
4197#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4198#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4199#define CAN_F1R2_FB15_Pos (15U)
4200#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4201#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4202#define CAN_F1R2_FB16_Pos (16U)
4203#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4204#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4205#define CAN_F1R2_FB17_Pos (17U)
4206#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4207#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4208#define CAN_F1R2_FB18_Pos (18U)
4209#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4210#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4211#define CAN_F1R2_FB19_Pos (19U)
4212#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4213#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4214#define CAN_F1R2_FB20_Pos (20U)
4215#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4216#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4217#define CAN_F1R2_FB21_Pos (21U)
4218#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4219#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4220#define CAN_F1R2_FB22_Pos (22U)
4221#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4222#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4223#define CAN_F1R2_FB23_Pos (23U)
4224#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4225#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4226#define CAN_F1R2_FB24_Pos (24U)
4227#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4228#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4229#define CAN_F1R2_FB25_Pos (25U)
4230#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4231#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4232#define CAN_F1R2_FB26_Pos (26U)
4233#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4234#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4235#define CAN_F1R2_FB27_Pos (27U)
4236#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4237#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4238#define CAN_F1R2_FB28_Pos (28U)
4239#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4240#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4241#define CAN_F1R2_FB29_Pos (29U)
4242#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4243#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4244#define CAN_F1R2_FB30_Pos (30U)
4245#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4246#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4247#define CAN_F1R2_FB31_Pos (31U)
4248#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4249#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4250
4251/******************* Bit definition for CAN_F2R2 register *******************/
4252#define CAN_F2R2_FB0_Pos (0U)
4253#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4254#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4255#define CAN_F2R2_FB1_Pos (1U)
4256#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4257#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4258#define CAN_F2R2_FB2_Pos (2U)
4259#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4260#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4261#define CAN_F2R2_FB3_Pos (3U)
4262#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4263#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4264#define CAN_F2R2_FB4_Pos (4U)
4265#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4266#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4267#define CAN_F2R2_FB5_Pos (5U)
4268#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4269#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4270#define CAN_F2R2_FB6_Pos (6U)
4271#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4272#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4273#define CAN_F2R2_FB7_Pos (7U)
4274#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4275#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4276#define CAN_F2R2_FB8_Pos (8U)
4277#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4278#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4279#define CAN_F2R2_FB9_Pos (9U)
4280#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4281#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4282#define CAN_F2R2_FB10_Pos (10U)
4283#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4284#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4285#define CAN_F2R2_FB11_Pos (11U)
4286#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4287#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4288#define CAN_F2R2_FB12_Pos (12U)
4289#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4290#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4291#define CAN_F2R2_FB13_Pos (13U)
4292#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4293#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4294#define CAN_F2R2_FB14_Pos (14U)
4295#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4296#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4297#define CAN_F2R2_FB15_Pos (15U)
4298#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4299#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4300#define CAN_F2R2_FB16_Pos (16U)
4301#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4302#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4303#define CAN_F2R2_FB17_Pos (17U)
4304#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4305#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4306#define CAN_F2R2_FB18_Pos (18U)
4307#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4308#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4309#define CAN_F2R2_FB19_Pos (19U)
4310#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4311#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4312#define CAN_F2R2_FB20_Pos (20U)
4313#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4314#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4315#define CAN_F2R2_FB21_Pos (21U)
4316#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4317#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4318#define CAN_F2R2_FB22_Pos (22U)
4319#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4320#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4321#define CAN_F2R2_FB23_Pos (23U)
4322#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4323#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4324#define CAN_F2R2_FB24_Pos (24U)
4325#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4326#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4327#define CAN_F2R2_FB25_Pos (25U)
4328#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4329#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4330#define CAN_F2R2_FB26_Pos (26U)
4331#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4332#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4333#define CAN_F2R2_FB27_Pos (27U)
4334#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4335#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4336#define CAN_F2R2_FB28_Pos (28U)
4337#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4338#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4339#define CAN_F2R2_FB29_Pos (29U)
4340#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4341#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4342#define CAN_F2R2_FB30_Pos (30U)
4343#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4344#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4345#define CAN_F2R2_FB31_Pos (31U)
4346#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4347#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4348
4349/******************* Bit definition for CAN_F3R2 register *******************/
4350#define CAN_F3R2_FB0_Pos (0U)
4351#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4352#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4353#define CAN_F3R2_FB1_Pos (1U)
4354#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4355#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4356#define CAN_F3R2_FB2_Pos (2U)
4357#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4358#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4359#define CAN_F3R2_FB3_Pos (3U)
4360#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4361#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4362#define CAN_F3R2_FB4_Pos (4U)
4363#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4364#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4365#define CAN_F3R2_FB5_Pos (5U)
4366#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4367#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4368#define CAN_F3R2_FB6_Pos (6U)
4369#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4370#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4371#define CAN_F3R2_FB7_Pos (7U)
4372#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4373#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4374#define CAN_F3R2_FB8_Pos (8U)
4375#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4376#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4377#define CAN_F3R2_FB9_Pos (9U)
4378#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4379#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4380#define CAN_F3R2_FB10_Pos (10U)
4381#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4382#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4383#define CAN_F3R2_FB11_Pos (11U)
4384#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4385#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4386#define CAN_F3R2_FB12_Pos (12U)
4387#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4388#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4389#define CAN_F3R2_FB13_Pos (13U)
4390#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4391#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4392#define CAN_F3R2_FB14_Pos (14U)
4393#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4394#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4395#define CAN_F3R2_FB15_Pos (15U)
4396#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4397#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4398#define CAN_F3R2_FB16_Pos (16U)
4399#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4400#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4401#define CAN_F3R2_FB17_Pos (17U)
4402#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4403#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4404#define CAN_F3R2_FB18_Pos (18U)
4405#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4406#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4407#define CAN_F3R2_FB19_Pos (19U)
4408#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4409#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4410#define CAN_F3R2_FB20_Pos (20U)
4411#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4412#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4413#define CAN_F3R2_FB21_Pos (21U)
4414#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4415#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4416#define CAN_F3R2_FB22_Pos (22U)
4417#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4418#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4419#define CAN_F3R2_FB23_Pos (23U)
4420#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4421#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4422#define CAN_F3R2_FB24_Pos (24U)
4423#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4424#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4425#define CAN_F3R2_FB25_Pos (25U)
4426#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4427#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4428#define CAN_F3R2_FB26_Pos (26U)
4429#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4430#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4431#define CAN_F3R2_FB27_Pos (27U)
4432#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4433#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4434#define CAN_F3R2_FB28_Pos (28U)
4435#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4436#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4437#define CAN_F3R2_FB29_Pos (29U)
4438#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4439#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4440#define CAN_F3R2_FB30_Pos (30U)
4441#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4442#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4443#define CAN_F3R2_FB31_Pos (31U)
4444#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4445#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4446
4447/******************* Bit definition for CAN_F4R2 register *******************/
4448#define CAN_F4R2_FB0_Pos (0U)
4449#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4450#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4451#define CAN_F4R2_FB1_Pos (1U)
4452#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4453#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4454#define CAN_F4R2_FB2_Pos (2U)
4455#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4456#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4457#define CAN_F4R2_FB3_Pos (3U)
4458#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4459#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4460#define CAN_F4R2_FB4_Pos (4U)
4461#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4462#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4463#define CAN_F4R2_FB5_Pos (5U)
4464#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4465#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4466#define CAN_F4R2_FB6_Pos (6U)
4467#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4468#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4469#define CAN_F4R2_FB7_Pos (7U)
4470#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4471#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4472#define CAN_F4R2_FB8_Pos (8U)
4473#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4474#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4475#define CAN_F4R2_FB9_Pos (9U)
4476#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4477#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4478#define CAN_F4R2_FB10_Pos (10U)
4479#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4480#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4481#define CAN_F4R2_FB11_Pos (11U)
4482#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4483#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4484#define CAN_F4R2_FB12_Pos (12U)
4485#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4486#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4487#define CAN_F4R2_FB13_Pos (13U)
4488#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4489#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4490#define CAN_F4R2_FB14_Pos (14U)
4491#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4492#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4493#define CAN_F4R2_FB15_Pos (15U)
4494#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4495#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4496#define CAN_F4R2_FB16_Pos (16U)
4497#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4498#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4499#define CAN_F4R2_FB17_Pos (17U)
4500#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4501#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4502#define CAN_F4R2_FB18_Pos (18U)
4503#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4504#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4505#define CAN_F4R2_FB19_Pos (19U)
4506#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4507#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4508#define CAN_F4R2_FB20_Pos (20U)
4509#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4510#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4511#define CAN_F4R2_FB21_Pos (21U)
4512#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4513#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4514#define CAN_F4R2_FB22_Pos (22U)
4515#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4516#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4517#define CAN_F4R2_FB23_Pos (23U)
4518#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4519#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4520#define CAN_F4R2_FB24_Pos (24U)
4521#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4522#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4523#define CAN_F4R2_FB25_Pos (25U)
4524#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4525#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4526#define CAN_F4R2_FB26_Pos (26U)
4527#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4528#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4529#define CAN_F4R2_FB27_Pos (27U)
4530#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4531#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4532#define CAN_F4R2_FB28_Pos (28U)
4533#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4534#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4535#define CAN_F4R2_FB29_Pos (29U)
4536#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4537#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4538#define CAN_F4R2_FB30_Pos (30U)
4539#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4540#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4541#define CAN_F4R2_FB31_Pos (31U)
4542#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4543#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4544
4545/******************* Bit definition for CAN_F5R2 register *******************/
4546#define CAN_F5R2_FB0_Pos (0U)
4547#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4548#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4549#define CAN_F5R2_FB1_Pos (1U)
4550#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4551#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4552#define CAN_F5R2_FB2_Pos (2U)
4553#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4554#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4555#define CAN_F5R2_FB3_Pos (3U)
4556#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4557#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4558#define CAN_F5R2_FB4_Pos (4U)
4559#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4560#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4561#define CAN_F5R2_FB5_Pos (5U)
4562#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4563#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4564#define CAN_F5R2_FB6_Pos (6U)
4565#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4566#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4567#define CAN_F5R2_FB7_Pos (7U)
4568#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4569#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4570#define CAN_F5R2_FB8_Pos (8U)
4571#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4572#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4573#define CAN_F5R2_FB9_Pos (9U)
4574#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4575#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4576#define CAN_F5R2_FB10_Pos (10U)
4577#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4578#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4579#define CAN_F5R2_FB11_Pos (11U)
4580#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4581#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4582#define CAN_F5R2_FB12_Pos (12U)
4583#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4584#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4585#define CAN_F5R2_FB13_Pos (13U)
4586#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4587#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4588#define CAN_F5R2_FB14_Pos (14U)
4589#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4590#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4591#define CAN_F5R2_FB15_Pos (15U)
4592#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4593#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4594#define CAN_F5R2_FB16_Pos (16U)
4595#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4596#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4597#define CAN_F5R2_FB17_Pos (17U)
4598#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4599#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4600#define CAN_F5R2_FB18_Pos (18U)
4601#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4602#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4603#define CAN_F5R2_FB19_Pos (19U)
4604#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4605#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4606#define CAN_F5R2_FB20_Pos (20U)
4607#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4608#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4609#define CAN_F5R2_FB21_Pos (21U)
4610#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4611#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4612#define CAN_F5R2_FB22_Pos (22U)
4613#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4614#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4615#define CAN_F5R2_FB23_Pos (23U)
4616#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4617#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4618#define CAN_F5R2_FB24_Pos (24U)
4619#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4620#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4621#define CAN_F5R2_FB25_Pos (25U)
4622#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4623#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4624#define CAN_F5R2_FB26_Pos (26U)
4625#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4626#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4627#define CAN_F5R2_FB27_Pos (27U)
4628#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4629#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4630#define CAN_F5R2_FB28_Pos (28U)
4631#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4632#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4633#define CAN_F5R2_FB29_Pos (29U)
4634#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4635#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4636#define CAN_F5R2_FB30_Pos (30U)
4637#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4638#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4639#define CAN_F5R2_FB31_Pos (31U)
4640#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4641#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4642
4643/******************* Bit definition for CAN_F6R2 register *******************/
4644#define CAN_F6R2_FB0_Pos (0U)
4645#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4646#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4647#define CAN_F6R2_FB1_Pos (1U)
4648#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4649#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4650#define CAN_F6R2_FB2_Pos (2U)
4651#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4652#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4653#define CAN_F6R2_FB3_Pos (3U)
4654#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4655#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4656#define CAN_F6R2_FB4_Pos (4U)
4657#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4658#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4659#define CAN_F6R2_FB5_Pos (5U)
4660#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4661#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4662#define CAN_F6R2_FB6_Pos (6U)
4663#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4664#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4665#define CAN_F6R2_FB7_Pos (7U)
4666#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4667#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4668#define CAN_F6R2_FB8_Pos (8U)
4669#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4670#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4671#define CAN_F6R2_FB9_Pos (9U)
4672#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4673#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4674#define CAN_F6R2_FB10_Pos (10U)
4675#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4676#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4677#define CAN_F6R2_FB11_Pos (11U)
4678#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4679#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4680#define CAN_F6R2_FB12_Pos (12U)
4681#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4682#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4683#define CAN_F6R2_FB13_Pos (13U)
4684#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4685#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4686#define CAN_F6R2_FB14_Pos (14U)
4687#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4688#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4689#define CAN_F6R2_FB15_Pos (15U)
4690#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4691#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4692#define CAN_F6R2_FB16_Pos (16U)
4693#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4694#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4695#define CAN_F6R2_FB17_Pos (17U)
4696#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4697#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4698#define CAN_F6R2_FB18_Pos (18U)
4699#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4700#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4701#define CAN_F6R2_FB19_Pos (19U)
4702#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4703#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4704#define CAN_F6R2_FB20_Pos (20U)
4705#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4706#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4707#define CAN_F6R2_FB21_Pos (21U)
4708#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4709#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4710#define CAN_F6R2_FB22_Pos (22U)
4711#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4712#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4713#define CAN_F6R2_FB23_Pos (23U)
4714#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4715#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4716#define CAN_F6R2_FB24_Pos (24U)
4717#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4718#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4719#define CAN_F6R2_FB25_Pos (25U)
4720#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4721#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4722#define CAN_F6R2_FB26_Pos (26U)
4723#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4724#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4725#define CAN_F6R2_FB27_Pos (27U)
4726#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4727#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4728#define CAN_F6R2_FB28_Pos (28U)
4729#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4730#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4731#define CAN_F6R2_FB29_Pos (29U)
4732#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4733#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4734#define CAN_F6R2_FB30_Pos (30U)
4735#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4736#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4737#define CAN_F6R2_FB31_Pos (31U)
4738#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4739#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4740
4741/******************* Bit definition for CAN_F7R2 register *******************/
4742#define CAN_F7R2_FB0_Pos (0U)
4743#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4744#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4745#define CAN_F7R2_FB1_Pos (1U)
4746#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4747#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4748#define CAN_F7R2_FB2_Pos (2U)
4749#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4750#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4751#define CAN_F7R2_FB3_Pos (3U)
4752#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4753#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4754#define CAN_F7R2_FB4_Pos (4U)
4755#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4756#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4757#define CAN_F7R2_FB5_Pos (5U)
4758#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4759#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4760#define CAN_F7R2_FB6_Pos (6U)
4761#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4762#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4763#define CAN_F7R2_FB7_Pos (7U)
4764#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4765#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4766#define CAN_F7R2_FB8_Pos (8U)
4767#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4768#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4769#define CAN_F7R2_FB9_Pos (9U)
4770#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4771#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4772#define CAN_F7R2_FB10_Pos (10U)
4773#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4774#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4775#define CAN_F7R2_FB11_Pos (11U)
4776#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4777#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4778#define CAN_F7R2_FB12_Pos (12U)
4779#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4780#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4781#define CAN_F7R2_FB13_Pos (13U)
4782#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4783#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4784#define CAN_F7R2_FB14_Pos (14U)
4785#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4786#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4787#define CAN_F7R2_FB15_Pos (15U)
4788#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4789#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4790#define CAN_F7R2_FB16_Pos (16U)
4791#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4792#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4793#define CAN_F7R2_FB17_Pos (17U)
4794#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4795#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4796#define CAN_F7R2_FB18_Pos (18U)
4797#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4798#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4799#define CAN_F7R2_FB19_Pos (19U)
4800#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4801#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4802#define CAN_F7R2_FB20_Pos (20U)
4803#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4804#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4805#define CAN_F7R2_FB21_Pos (21U)
4806#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4807#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4808#define CAN_F7R2_FB22_Pos (22U)
4809#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4810#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4811#define CAN_F7R2_FB23_Pos (23U)
4812#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4813#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4814#define CAN_F7R2_FB24_Pos (24U)
4815#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4816#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4817#define CAN_F7R2_FB25_Pos (25U)
4818#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4819#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4820#define CAN_F7R2_FB26_Pos (26U)
4821#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4822#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4823#define CAN_F7R2_FB27_Pos (27U)
4824#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4825#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4826#define CAN_F7R2_FB28_Pos (28U)
4827#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4828#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4829#define CAN_F7R2_FB29_Pos (29U)
4830#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4831#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4832#define CAN_F7R2_FB30_Pos (30U)
4833#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4834#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4835#define CAN_F7R2_FB31_Pos (31U)
4836#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4837#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4838
4839/******************* Bit definition for CAN_F8R2 register *******************/
4840#define CAN_F8R2_FB0_Pos (0U)
4841#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4842#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4843#define CAN_F8R2_FB1_Pos (1U)
4844#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4845#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4846#define CAN_F8R2_FB2_Pos (2U)
4847#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4848#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4849#define CAN_F8R2_FB3_Pos (3U)
4850#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4851#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4852#define CAN_F8R2_FB4_Pos (4U)
4853#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4854#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4855#define CAN_F8R2_FB5_Pos (5U)
4856#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4857#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4858#define CAN_F8R2_FB6_Pos (6U)
4859#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4860#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4861#define CAN_F8R2_FB7_Pos (7U)
4862#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4863#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4864#define CAN_F8R2_FB8_Pos (8U)
4865#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4866#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4867#define CAN_F8R2_FB9_Pos (9U)
4868#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4869#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4870#define CAN_F8R2_FB10_Pos (10U)
4871#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4872#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4873#define CAN_F8R2_FB11_Pos (11U)
4874#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4875#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4876#define CAN_F8R2_FB12_Pos (12U)
4877#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4878#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4879#define CAN_F8R2_FB13_Pos (13U)
4880#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4881#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4882#define CAN_F8R2_FB14_Pos (14U)
4883#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4884#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4885#define CAN_F8R2_FB15_Pos (15U)
4886#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4887#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4888#define CAN_F8R2_FB16_Pos (16U)
4889#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4890#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4891#define CAN_F8R2_FB17_Pos (17U)
4892#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4893#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4894#define CAN_F8R2_FB18_Pos (18U)
4895#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4896#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4897#define CAN_F8R2_FB19_Pos (19U)
4898#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4899#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4900#define CAN_F8R2_FB20_Pos (20U)
4901#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4902#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4903#define CAN_F8R2_FB21_Pos (21U)
4904#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4905#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4906#define CAN_F8R2_FB22_Pos (22U)
4907#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4908#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4909#define CAN_F8R2_FB23_Pos (23U)
4910#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4911#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4912#define CAN_F8R2_FB24_Pos (24U)
4913#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4914#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4915#define CAN_F8R2_FB25_Pos (25U)
4916#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4917#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4918#define CAN_F8R2_FB26_Pos (26U)
4919#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4920#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4921#define CAN_F8R2_FB27_Pos (27U)
4922#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4923#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4924#define CAN_F8R2_FB28_Pos (28U)
4925#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4926#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4927#define CAN_F8R2_FB29_Pos (29U)
4928#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4929#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4930#define CAN_F8R2_FB30_Pos (30U)
4931#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4932#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4933#define CAN_F8R2_FB31_Pos (31U)
4934#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4935#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4936
4937/******************* Bit definition for CAN_F9R2 register *******************/
4938#define CAN_F9R2_FB0_Pos (0U)
4939#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4940#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4941#define CAN_F9R2_FB1_Pos (1U)
4942#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4943#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4944#define CAN_F9R2_FB2_Pos (2U)
4945#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4946#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4947#define CAN_F9R2_FB3_Pos (3U)
4948#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4949#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4950#define CAN_F9R2_FB4_Pos (4U)
4951#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4952#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4953#define CAN_F9R2_FB5_Pos (5U)
4954#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4955#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4956#define CAN_F9R2_FB6_Pos (6U)
4957#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4958#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4959#define CAN_F9R2_FB7_Pos (7U)
4960#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4961#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4962#define CAN_F9R2_FB8_Pos (8U)
4963#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4964#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4965#define CAN_F9R2_FB9_Pos (9U)
4966#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4967#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4968#define CAN_F9R2_FB10_Pos (10U)
4969#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4970#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4971#define CAN_F9R2_FB11_Pos (11U)
4972#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4973#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4974#define CAN_F9R2_FB12_Pos (12U)
4975#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4976#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4977#define CAN_F9R2_FB13_Pos (13U)
4978#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4979#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4980#define CAN_F9R2_FB14_Pos (14U)
4981#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4982#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4983#define CAN_F9R2_FB15_Pos (15U)
4984#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4985#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4986#define CAN_F9R2_FB16_Pos (16U)
4987#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4988#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4989#define CAN_F9R2_FB17_Pos (17U)
4990#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4991#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4992#define CAN_F9R2_FB18_Pos (18U)
4993#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4994#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4995#define CAN_F9R2_FB19_Pos (19U)
4996#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4997#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4998#define CAN_F9R2_FB20_Pos (20U)
4999#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5000#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5001#define CAN_F9R2_FB21_Pos (21U)
5002#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5003#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5004#define CAN_F9R2_FB22_Pos (22U)
5005#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5006#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5007#define CAN_F9R2_FB23_Pos (23U)
5008#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5009#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5010#define CAN_F9R2_FB24_Pos (24U)
5011#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5012#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5013#define CAN_F9R2_FB25_Pos (25U)
5014#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5015#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5016#define CAN_F9R2_FB26_Pos (26U)
5017#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5018#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5019#define CAN_F9R2_FB27_Pos (27U)
5020#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5021#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5022#define CAN_F9R2_FB28_Pos (28U)
5023#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5024#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5025#define CAN_F9R2_FB29_Pos (29U)
5026#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5027#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5028#define CAN_F9R2_FB30_Pos (30U)
5029#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5030#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5031#define CAN_F9R2_FB31_Pos (31U)
5032#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5033#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5034
5035/******************* Bit definition for CAN_F10R2 register ******************/
5036#define CAN_F10R2_FB0_Pos (0U)
5037#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5038#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5039#define CAN_F10R2_FB1_Pos (1U)
5040#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5041#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5042#define CAN_F10R2_FB2_Pos (2U)
5043#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5044#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5045#define CAN_F10R2_FB3_Pos (3U)
5046#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5047#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5048#define CAN_F10R2_FB4_Pos (4U)
5049#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5050#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5051#define CAN_F10R2_FB5_Pos (5U)
5052#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5053#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5054#define CAN_F10R2_FB6_Pos (6U)
5055#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5056#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5057#define CAN_F10R2_FB7_Pos (7U)
5058#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5059#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5060#define CAN_F10R2_FB8_Pos (8U)
5061#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5062#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5063#define CAN_F10R2_FB9_Pos (9U)
5064#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5065#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5066#define CAN_F10R2_FB10_Pos (10U)
5067#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5068#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5069#define CAN_F10R2_FB11_Pos (11U)
5070#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5071#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5072#define CAN_F10R2_FB12_Pos (12U)
5073#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5074#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5075#define CAN_F10R2_FB13_Pos (13U)
5076#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5077#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5078#define CAN_F10R2_FB14_Pos (14U)
5079#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5080#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5081#define CAN_F10R2_FB15_Pos (15U)
5082#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5083#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5084#define CAN_F10R2_FB16_Pos (16U)
5085#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5086#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5087#define CAN_F10R2_FB17_Pos (17U)
5088#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5089#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5090#define CAN_F10R2_FB18_Pos (18U)
5091#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5092#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5093#define CAN_F10R2_FB19_Pos (19U)
5094#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5095#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5096#define CAN_F10R2_FB20_Pos (20U)
5097#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5098#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5099#define CAN_F10R2_FB21_Pos (21U)
5100#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5101#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5102#define CAN_F10R2_FB22_Pos (22U)
5103#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5104#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5105#define CAN_F10R2_FB23_Pos (23U)
5106#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5107#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5108#define CAN_F10R2_FB24_Pos (24U)
5109#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5110#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5111#define CAN_F10R2_FB25_Pos (25U)
5112#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5113#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5114#define CAN_F10R2_FB26_Pos (26U)
5115#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5116#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5117#define CAN_F10R2_FB27_Pos (27U)
5118#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5119#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5120#define CAN_F10R2_FB28_Pos (28U)
5121#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5122#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5123#define CAN_F10R2_FB29_Pos (29U)
5124#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5125#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5126#define CAN_F10R2_FB30_Pos (30U)
5127#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5128#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5129#define CAN_F10R2_FB31_Pos (31U)
5130#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5131#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5132
5133/******************* Bit definition for CAN_F11R2 register ******************/
5134#define CAN_F11R2_FB0_Pos (0U)
5135#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5136#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5137#define CAN_F11R2_FB1_Pos (1U)
5138#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5139#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5140#define CAN_F11R2_FB2_Pos (2U)
5141#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5142#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5143#define CAN_F11R2_FB3_Pos (3U)
5144#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5145#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5146#define CAN_F11R2_FB4_Pos (4U)
5147#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5148#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5149#define CAN_F11R2_FB5_Pos (5U)
5150#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5151#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5152#define CAN_F11R2_FB6_Pos (6U)
5153#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5154#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5155#define CAN_F11R2_FB7_Pos (7U)
5156#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5157#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5158#define CAN_F11R2_FB8_Pos (8U)
5159#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5160#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5161#define CAN_F11R2_FB9_Pos (9U)
5162#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5163#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5164#define CAN_F11R2_FB10_Pos (10U)
5165#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5166#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5167#define CAN_F11R2_FB11_Pos (11U)
5168#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5169#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5170#define CAN_F11R2_FB12_Pos (12U)
5171#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5172#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5173#define CAN_F11R2_FB13_Pos (13U)
5174#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5175#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5176#define CAN_F11R2_FB14_Pos (14U)
5177#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5178#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5179#define CAN_F11R2_FB15_Pos (15U)
5180#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5181#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5182#define CAN_F11R2_FB16_Pos (16U)
5183#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5184#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5185#define CAN_F11R2_FB17_Pos (17U)
5186#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5187#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5188#define CAN_F11R2_FB18_Pos (18U)
5189#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5190#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5191#define CAN_F11R2_FB19_Pos (19U)
5192#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5193#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5194#define CAN_F11R2_FB20_Pos (20U)
5195#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5196#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5197#define CAN_F11R2_FB21_Pos (21U)
5198#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5199#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5200#define CAN_F11R2_FB22_Pos (22U)
5201#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5202#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5203#define CAN_F11R2_FB23_Pos (23U)
5204#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5205#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5206#define CAN_F11R2_FB24_Pos (24U)
5207#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5208#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5209#define CAN_F11R2_FB25_Pos (25U)
5210#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5211#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5212#define CAN_F11R2_FB26_Pos (26U)
5213#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5214#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5215#define CAN_F11R2_FB27_Pos (27U)
5216#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5217#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5218#define CAN_F11R2_FB28_Pos (28U)
5219#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5220#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5221#define CAN_F11R2_FB29_Pos (29U)
5222#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5223#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5224#define CAN_F11R2_FB30_Pos (30U)
5225#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5226#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5227#define CAN_F11R2_FB31_Pos (31U)
5228#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5229#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5230
5231/******************* Bit definition for CAN_F12R2 register ******************/
5232#define CAN_F12R2_FB0_Pos (0U)
5233#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5234#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5235#define CAN_F12R2_FB1_Pos (1U)
5236#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5237#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5238#define CAN_F12R2_FB2_Pos (2U)
5239#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5240#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5241#define CAN_F12R2_FB3_Pos (3U)
5242#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5243#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5244#define CAN_F12R2_FB4_Pos (4U)
5245#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5246#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5247#define CAN_F12R2_FB5_Pos (5U)
5248#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5249#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5250#define CAN_F12R2_FB6_Pos (6U)
5251#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5252#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5253#define CAN_F12R2_FB7_Pos (7U)
5254#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5255#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5256#define CAN_F12R2_FB8_Pos (8U)
5257#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5258#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5259#define CAN_F12R2_FB9_Pos (9U)
5260#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5261#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5262#define CAN_F12R2_FB10_Pos (10U)
5263#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5264#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5265#define CAN_F12R2_FB11_Pos (11U)
5266#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5267#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5268#define CAN_F12R2_FB12_Pos (12U)
5269#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5270#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5271#define CAN_F12R2_FB13_Pos (13U)
5272#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5273#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5274#define CAN_F12R2_FB14_Pos (14U)
5275#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5276#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5277#define CAN_F12R2_FB15_Pos (15U)
5278#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5279#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5280#define CAN_F12R2_FB16_Pos (16U)
5281#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5282#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5283#define CAN_F12R2_FB17_Pos (17U)
5284#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5285#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5286#define CAN_F12R2_FB18_Pos (18U)
5287#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5288#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5289#define CAN_F12R2_FB19_Pos (19U)
5290#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5291#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5292#define CAN_F12R2_FB20_Pos (20U)
5293#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5294#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5295#define CAN_F12R2_FB21_Pos (21U)
5296#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5297#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5298#define CAN_F12R2_FB22_Pos (22U)
5299#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5300#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5301#define CAN_F12R2_FB23_Pos (23U)
5302#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5303#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5304#define CAN_F12R2_FB24_Pos (24U)
5305#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5306#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5307#define CAN_F12R2_FB25_Pos (25U)
5308#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5309#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5310#define CAN_F12R2_FB26_Pos (26U)
5311#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5312#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5313#define CAN_F12R2_FB27_Pos (27U)
5314#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5315#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5316#define CAN_F12R2_FB28_Pos (28U)
5317#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5318#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5319#define CAN_F12R2_FB29_Pos (29U)
5320#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5321#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5322#define CAN_F12R2_FB30_Pos (30U)
5323#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5324#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5325#define CAN_F12R2_FB31_Pos (31U)
5326#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5327#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5328
5329/******************* Bit definition for CAN_F13R2 register ******************/
5330#define CAN_F13R2_FB0_Pos (0U)
5331#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5332#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5333#define CAN_F13R2_FB1_Pos (1U)
5334#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5335#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5336#define CAN_F13R2_FB2_Pos (2U)
5337#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5338#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5339#define CAN_F13R2_FB3_Pos (3U)
5340#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5341#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5342#define CAN_F13R2_FB4_Pos (4U)
5343#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5344#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5345#define CAN_F13R2_FB5_Pos (5U)
5346#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5347#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5348#define CAN_F13R2_FB6_Pos (6U)
5349#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5350#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5351#define CAN_F13R2_FB7_Pos (7U)
5352#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5353#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5354#define CAN_F13R2_FB8_Pos (8U)
5355#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5356#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5357#define CAN_F13R2_FB9_Pos (9U)
5358#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5359#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5360#define CAN_F13R2_FB10_Pos (10U)
5361#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5362#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5363#define CAN_F13R2_FB11_Pos (11U)
5364#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5365#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5366#define CAN_F13R2_FB12_Pos (12U)
5367#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5368#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5369#define CAN_F13R2_FB13_Pos (13U)
5370#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5371#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5372#define CAN_F13R2_FB14_Pos (14U)
5373#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5374#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5375#define CAN_F13R2_FB15_Pos (15U)
5376#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5377#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5378#define CAN_F13R2_FB16_Pos (16U)
5379#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5380#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5381#define CAN_F13R2_FB17_Pos (17U)
5382#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5383#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5384#define CAN_F13R2_FB18_Pos (18U)
5385#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5386#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5387#define CAN_F13R2_FB19_Pos (19U)
5388#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5389#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5390#define CAN_F13R2_FB20_Pos (20U)
5391#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5392#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5393#define CAN_F13R2_FB21_Pos (21U)
5394#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5395#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5396#define CAN_F13R2_FB22_Pos (22U)
5397#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5398#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5399#define CAN_F13R2_FB23_Pos (23U)
5400#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5401#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5402#define CAN_F13R2_FB24_Pos (24U)
5403#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5404#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5405#define CAN_F13R2_FB25_Pos (25U)
5406#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5407#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5408#define CAN_F13R2_FB26_Pos (26U)
5409#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5410#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5411#define CAN_F13R2_FB27_Pos (27U)
5412#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5413#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5414#define CAN_F13R2_FB28_Pos (28U)
5415#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5416#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5417#define CAN_F13R2_FB29_Pos (29U)
5418#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5419#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5420#define CAN_F13R2_FB30_Pos (30U)
5421#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5422#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5423#define CAN_F13R2_FB31_Pos (31U)
5424#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5425#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5426
5427/******************************************************************************/
5428/* */
5429/* CRC calculation unit */
5430/* */
5431/******************************************************************************/
5432/******************* Bit definition for CRC_DR register *********************/
5433#define CRC_DR_DR_Pos (0U)
5434#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5435#define CRC_DR_DR CRC_DR_DR_Msk
5436
5437
5438/******************* Bit definition for CRC_IDR register ********************/
5439#define CRC_IDR_IDR_Pos (0U)
5440#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5441#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5442
5443
5444/******************** Bit definition for CRC_CR register ********************/
5445#define CRC_CR_RESET_Pos (0U)
5446#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5447#define CRC_CR_RESET CRC_CR_RESET_Msk
5448
5449/******************************************************************************/
5450/* */
5451/* Digital to Analog Converter */
5452/* */
5453/******************************************************************************/
5454/*
5455 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
5456 */
5457#define DAC_CHANNEL2_SUPPORT
5458/******************** Bit definition for DAC_CR register ********************/
5459#define DAC_CR_EN1_Pos (0U)
5460#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5461#define DAC_CR_EN1 DAC_CR_EN1_Msk
5462#define DAC_CR_BOFF1_Pos (1U)
5463#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5464#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5465#define DAC_CR_TEN1_Pos (2U)
5466#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5467#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5468
5469#define DAC_CR_TSEL1_Pos (3U)
5470#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5471#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5472#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5473#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5474#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5475
5476#define DAC_CR_WAVE1_Pos (6U)
5477#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5478#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5479#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5480#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5481
5482#define DAC_CR_MAMP1_Pos (8U)
5483#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5484#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5485#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5486#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5487#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5488#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5489
5490#define DAC_CR_DMAEN1_Pos (12U)
5491#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5492#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5493#define DAC_CR_DMAUDRIE1_Pos (13U)
5494#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5495#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5496#define DAC_CR_EN2_Pos (16U)
5497#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5498#define DAC_CR_EN2 DAC_CR_EN2_Msk
5499#define DAC_CR_BOFF2_Pos (17U)
5500#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5501#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5502#define DAC_CR_TEN2_Pos (18U)
5503#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5504#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5505
5506#define DAC_CR_TSEL2_Pos (19U)
5507#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5508#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5509#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5510#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5511#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5512
5513#define DAC_CR_WAVE2_Pos (22U)
5514#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5515#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5516#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5517#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5518
5519#define DAC_CR_MAMP2_Pos (24U)
5520#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5521#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5522#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5523#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5524#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5525#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5526
5527#define DAC_CR_DMAEN2_Pos (28U)
5528#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5529#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5530#define DAC_CR_DMAUDRIE2_Pos (29U)
5531#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5532#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5533
5534/***************** Bit definition for DAC_SWTRIGR register ******************/
5535#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5536#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5537#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5538#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5539#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5540#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5541
5542/***************** Bit definition for DAC_DHR12R1 register ******************/
5543#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5544#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5545#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5546
5547/***************** Bit definition for DAC_DHR12L1 register ******************/
5548#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5549#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5550#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5551
5552/****************** Bit definition for DAC_DHR8R1 register ******************/
5553#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5554#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5555#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5556
5557/***************** Bit definition for DAC_DHR12R2 register ******************/
5558#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5559#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5560#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5561
5562/***************** Bit definition for DAC_DHR12L2 register ******************/
5563#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5564#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5565#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5566
5567/****************** Bit definition for DAC_DHR8R2 register ******************/
5568#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5569#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5570#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5571
5572/***************** Bit definition for DAC_DHR12RD register ******************/
5573#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5574#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5575#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5576#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5577#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5578#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5579
5580/***************** Bit definition for DAC_DHR12LD register ******************/
5581#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5582#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5583#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5584#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5585#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5586#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5587
5588/****************** Bit definition for DAC_DHR8RD register ******************/
5589#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5590#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5591#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5592#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5593#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5594#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5595
5596/******************* Bit definition for DAC_DOR1 register *******************/
5597#define DAC_DOR1_DACC1DOR_Pos (0U)
5598#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5599#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5600
5601/******************* Bit definition for DAC_DOR2 register *******************/
5602#define DAC_DOR2_DACC2DOR_Pos (0U)
5603#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5604#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5605
5606/******************** Bit definition for DAC_SR register ********************/
5607#define DAC_SR_DMAUDR1_Pos (13U)
5608#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5609#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5610#define DAC_SR_DMAUDR2_Pos (29U)
5611#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5612#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5613
5614/******************************************************************************/
5615/* */
5616/* Digital Filter for Sigma Delta Modulators */
5617/* */
5618/******************************************************************************/
5619
5620/**************** DFSDM channel configuration registers ********************/
5621
5622/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5623#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5624#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
5625#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
5626#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5627#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
5628#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
5629#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5630#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
5631#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
5632#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5633#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
5634#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
5635#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
5636#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
5637#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5638#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
5639#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
5640#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
5641#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
5642#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5643#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
5644#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
5645#define DFSDM_CHCFGR1_CHEN_Pos (7U)
5646#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
5647#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
5648#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5649#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
5650#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
5651#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5652#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
5653#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
5654#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5655#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5656#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
5657#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5658#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5659#define DFSDM_CHCFGR1_SITP_Pos (0U)
5660#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
5661#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
5662#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
5663#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
5664
5665/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5666#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5667#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
5668#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
5669#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
5670#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
5671#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
5672
5673/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
5674#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
5675#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5676#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
5677#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5678#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5679#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
5680#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
5681#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
5682#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
5683#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
5684#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
5685#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
5686#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
5687#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
5688
5689/**************** Bit definition for DFSDM_CHWDATR register *******************/
5690#define DFSDM_CHWDATR_WDATA_Pos (0U)
5691#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
5692#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
5693
5694/**************** Bit definition for DFSDM_CHDATINR register *****************/
5695#define DFSDM_CHDATINR_INDAT0_Pos (0U)
5696#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
5697#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
5698#define DFSDM_CHDATINR_INDAT1_Pos (16U)
5699#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
5700#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
5701
5702/************************ DFSDM module registers ****************************/
5703
5704/***************** Bit definition for DFSDM_FLTCR1 register *******************/
5705#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
5706#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
5707#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
5708#define DFSDM_FLTCR1_FAST_Pos (29U)
5709#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
5710#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
5711#define DFSDM_FLTCR1_RCH_Pos (24U)
5712#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
5713#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
5714#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
5715#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
5716#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
5717#define DFSDM_FLTCR1_RSYNC_Pos (19U)
5718#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
5719#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
5720#define DFSDM_FLTCR1_RCONT_Pos (18U)
5721#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
5722#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
5723#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
5724#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
5725#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
5726#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
5727#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
5728#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
5729#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
5730#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
5731#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
5732#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5733#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
5734#define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5735#define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5736#define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5737#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
5738#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
5739#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
5740#define DFSDM_FLTCR1_JSCAN_Pos (4U)
5741#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
5742#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
5743#define DFSDM_FLTCR1_JSYNC_Pos (3U)
5744#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
5745#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
5746#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
5747#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
5748#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
5749#define DFSDM_FLTCR1_DFEN_Pos (0U)
5750#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
5751#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
5752
5753/***************** Bit definition for DFSDM_FLTCR2 register *******************/
5754#define DFSDM_FLTCR2_AWDCH_Pos (16U)
5755#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
5756#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
5757#define DFSDM_FLTCR2_EXCH_Pos (8U)
5758#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
5759#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
5760#define DFSDM_FLTCR2_CKABIE_Pos (6U)
5761#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
5762#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
5763#define DFSDM_FLTCR2_SCDIE_Pos (5U)
5764#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
5765#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
5766#define DFSDM_FLTCR2_AWDIE_Pos (4U)
5767#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
5768#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
5769#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
5770#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
5771#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
5772#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
5773#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
5774#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
5775#define DFSDM_FLTCR2_REOCIE_Pos (1U)
5776#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
5777#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
5778#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
5779#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
5780#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
5781
5782/***************** Bit definition for DFSDM_FLTISR register *******************/
5783#define DFSDM_FLTISR_SCDF_Pos (24U)
5784#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
5785#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
5786#define DFSDM_FLTISR_CKABF_Pos (16U)
5787#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
5788#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
5789#define DFSDM_FLTISR_RCIP_Pos (14U)
5790#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
5791#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
5792#define DFSDM_FLTISR_JCIP_Pos (13U)
5793#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
5794#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
5795#define DFSDM_FLTISR_AWDF_Pos (4U)
5796#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
5797#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
5798#define DFSDM_FLTISR_ROVRF_Pos (3U)
5799#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
5800#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
5801#define DFSDM_FLTISR_JOVRF_Pos (2U)
5802#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
5803#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
5804#define DFSDM_FLTISR_REOCF_Pos (1U)
5805#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
5806#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
5807#define DFSDM_FLTISR_JEOCF_Pos (0U)
5808#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
5809#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
5810
5811/***************** Bit definition for DFSDM_FLTICR register *******************/
5812#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
5813#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
5814#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
5815#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
5816#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
5817#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
5818#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
5819#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
5820#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
5821#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
5822#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
5823#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
5824
5825/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
5826#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
5827#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
5828#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
5829
5830/***************** Bit definition for DFSDM_FLTFCR register *******************/
5831#define DFSDM_FLTFCR_FORD_Pos (29U)
5832#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
5833#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
5834#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
5835#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
5836#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
5837#define DFSDM_FLTFCR_FOSR_Pos (16U)
5838#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
5839#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
5840#define DFSDM_FLTFCR_IOSR_Pos (0U)
5841#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
5842#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
5843
5844/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
5845#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
5846#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
5847#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
5848#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
5849#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
5850#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
5851
5852/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
5853#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
5854#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
5855#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
5856#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
5857#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
5858#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
5859#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
5860#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
5861#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
5862
5863/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
5864#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
5865#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
5866#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
5867#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
5868#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
5869#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
5870
5871/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
5872#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
5873#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
5874#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
5875#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
5876#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
5877#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
5878
5879/*************** Bit definition for DFSDM_FLTAWSR register *******************/
5880#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
5881#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
5882#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
5883#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
5884#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
5885#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
5886
5887
5888/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
5889#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
5890#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
5891#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
5892#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
5893#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
5894#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
5895
5896/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
5897#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
5898#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
5899#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
5900#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
5901#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
5902#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
5903
5904/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
5905#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
5906#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
5907#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
5908#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
5909#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
5910#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
5911
5912/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
5913#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
5914#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
5915#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
5916
5917/* Legacy Defines */
5918#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5919#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
5920#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
5921
5922/******************************************************************************/
5923/* */
5924/* DMA Controller */
5925/* */
5926/******************************************************************************/
5927/******************** Bits definition for DMA_SxCR register *****************/
5928#define DMA_SxCR_CHSEL_Pos (25U)
5929#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos)
5930#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5931#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5932#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5933#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5934#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos)
5935#define DMA_SxCR_MBURST_Pos (23U)
5936#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5937#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5938#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5939#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5940#define DMA_SxCR_PBURST_Pos (21U)
5941#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5942#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5943#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5944#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5945#define DMA_SxCR_CT_Pos (19U)
5946#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5947#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5948#define DMA_SxCR_DBM_Pos (18U)
5949#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5950#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5951#define DMA_SxCR_PL_Pos (16U)
5952#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5953#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5954#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5955#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5956#define DMA_SxCR_PINCOS_Pos (15U)
5957#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5958#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5959#define DMA_SxCR_MSIZE_Pos (13U)
5960#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5961#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5962#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5963#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5964#define DMA_SxCR_PSIZE_Pos (11U)
5965#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5966#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5967#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5968#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5969#define DMA_SxCR_MINC_Pos (10U)
5970#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5971#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5972#define DMA_SxCR_PINC_Pos (9U)
5973#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5974#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5975#define DMA_SxCR_CIRC_Pos (8U)
5976#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5977#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5978#define DMA_SxCR_DIR_Pos (6U)
5979#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5980#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5981#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5982#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5983#define DMA_SxCR_PFCTRL_Pos (5U)
5984#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5985#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5986#define DMA_SxCR_TCIE_Pos (4U)
5987#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5988#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5989#define DMA_SxCR_HTIE_Pos (3U)
5990#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5991#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5992#define DMA_SxCR_TEIE_Pos (2U)
5993#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5994#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5995#define DMA_SxCR_DMEIE_Pos (1U)
5996#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5997#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5998#define DMA_SxCR_EN_Pos (0U)
5999#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6000#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6001
6002/* Legacy defines */
6003#define DMA_SxCR_ACK_Pos (20U)
6004#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6005#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6006
6007/******************** Bits definition for DMA_SxCNDTR register **************/
6008#define DMA_SxNDT_Pos (0U)
6009#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6010#define DMA_SxNDT DMA_SxNDT_Msk
6011#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6012#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6013#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6014#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6015#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6016#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6017#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6018#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6019#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6020#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6021#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6022#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6023#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6024#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6025#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6026#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6027
6028/******************** Bits definition for DMA_SxFCR register ****************/
6029#define DMA_SxFCR_FEIE_Pos (7U)
6030#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6031#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6032#define DMA_SxFCR_FS_Pos (3U)
6033#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6034#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6035#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6036#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6037#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6038#define DMA_SxFCR_DMDIS_Pos (2U)
6039#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6040#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6041#define DMA_SxFCR_FTH_Pos (0U)
6042#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6043#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6044#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6045#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6046
6047/******************** Bits definition for DMA_LISR register *****************/
6048#define DMA_LISR_TCIF3_Pos (27U)
6049#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6050#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6051#define DMA_LISR_HTIF3_Pos (26U)
6052#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6053#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6054#define DMA_LISR_TEIF3_Pos (25U)
6055#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6056#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6057#define DMA_LISR_DMEIF3_Pos (24U)
6058#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6059#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6060#define DMA_LISR_FEIF3_Pos (22U)
6061#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6062#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6063#define DMA_LISR_TCIF2_Pos (21U)
6064#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6065#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6066#define DMA_LISR_HTIF2_Pos (20U)
6067#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6068#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6069#define DMA_LISR_TEIF2_Pos (19U)
6070#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6071#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6072#define DMA_LISR_DMEIF2_Pos (18U)
6073#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6074#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6075#define DMA_LISR_FEIF2_Pos (16U)
6076#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6077#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6078#define DMA_LISR_TCIF1_Pos (11U)
6079#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6080#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6081#define DMA_LISR_HTIF1_Pos (10U)
6082#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6083#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6084#define DMA_LISR_TEIF1_Pos (9U)
6085#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6086#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6087#define DMA_LISR_DMEIF1_Pos (8U)
6088#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6089#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6090#define DMA_LISR_FEIF1_Pos (6U)
6091#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6092#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6093#define DMA_LISR_TCIF0_Pos (5U)
6094#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6095#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6096#define DMA_LISR_HTIF0_Pos (4U)
6097#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6098#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6099#define DMA_LISR_TEIF0_Pos (3U)
6100#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6101#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6102#define DMA_LISR_DMEIF0_Pos (2U)
6103#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6104#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6105#define DMA_LISR_FEIF0_Pos (0U)
6106#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6107#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6108
6109/******************** Bits definition for DMA_HISR register *****************/
6110#define DMA_HISR_TCIF7_Pos (27U)
6111#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6112#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6113#define DMA_HISR_HTIF7_Pos (26U)
6114#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6115#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6116#define DMA_HISR_TEIF7_Pos (25U)
6117#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6118#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6119#define DMA_HISR_DMEIF7_Pos (24U)
6120#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6121#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6122#define DMA_HISR_FEIF7_Pos (22U)
6123#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6124#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6125#define DMA_HISR_TCIF6_Pos (21U)
6126#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6127#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6128#define DMA_HISR_HTIF6_Pos (20U)
6129#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6130#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6131#define DMA_HISR_TEIF6_Pos (19U)
6132#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6133#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6134#define DMA_HISR_DMEIF6_Pos (18U)
6135#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6136#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6137#define DMA_HISR_FEIF6_Pos (16U)
6138#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6139#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6140#define DMA_HISR_TCIF5_Pos (11U)
6141#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6142#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6143#define DMA_HISR_HTIF5_Pos (10U)
6144#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6145#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6146#define DMA_HISR_TEIF5_Pos (9U)
6147#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6148#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6149#define DMA_HISR_DMEIF5_Pos (8U)
6150#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6151#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6152#define DMA_HISR_FEIF5_Pos (6U)
6153#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6154#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6155#define DMA_HISR_TCIF4_Pos (5U)
6156#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6157#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6158#define DMA_HISR_HTIF4_Pos (4U)
6159#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6160#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6161#define DMA_HISR_TEIF4_Pos (3U)
6162#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6163#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6164#define DMA_HISR_DMEIF4_Pos (2U)
6165#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6166#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6167#define DMA_HISR_FEIF4_Pos (0U)
6168#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6169#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6170
6171/******************** Bits definition for DMA_LIFCR register ****************/
6172#define DMA_LIFCR_CTCIF3_Pos (27U)
6173#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6174#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6175#define DMA_LIFCR_CHTIF3_Pos (26U)
6176#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6177#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6178#define DMA_LIFCR_CTEIF3_Pos (25U)
6179#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6180#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6181#define DMA_LIFCR_CDMEIF3_Pos (24U)
6182#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6183#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6184#define DMA_LIFCR_CFEIF3_Pos (22U)
6185#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6186#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6187#define DMA_LIFCR_CTCIF2_Pos (21U)
6188#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6189#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6190#define DMA_LIFCR_CHTIF2_Pos (20U)
6191#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6192#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6193#define DMA_LIFCR_CTEIF2_Pos (19U)
6194#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6195#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6196#define DMA_LIFCR_CDMEIF2_Pos (18U)
6197#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6198#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6199#define DMA_LIFCR_CFEIF2_Pos (16U)
6200#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6201#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6202#define DMA_LIFCR_CTCIF1_Pos (11U)
6203#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6204#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6205#define DMA_LIFCR_CHTIF1_Pos (10U)
6206#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6207#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6208#define DMA_LIFCR_CTEIF1_Pos (9U)
6209#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6210#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6211#define DMA_LIFCR_CDMEIF1_Pos (8U)
6212#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6213#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6214#define DMA_LIFCR_CFEIF1_Pos (6U)
6215#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6216#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6217#define DMA_LIFCR_CTCIF0_Pos (5U)
6218#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6219#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6220#define DMA_LIFCR_CHTIF0_Pos (4U)
6221#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6222#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6223#define DMA_LIFCR_CTEIF0_Pos (3U)
6224#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6225#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6226#define DMA_LIFCR_CDMEIF0_Pos (2U)
6227#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6228#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6229#define DMA_LIFCR_CFEIF0_Pos (0U)
6230#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6231#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6232
6233/******************** Bits definition for DMA_HIFCR register ****************/
6234#define DMA_HIFCR_CTCIF7_Pos (27U)
6235#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6236#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6237#define DMA_HIFCR_CHTIF7_Pos (26U)
6238#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6239#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6240#define DMA_HIFCR_CTEIF7_Pos (25U)
6241#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6242#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6243#define DMA_HIFCR_CDMEIF7_Pos (24U)
6244#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6245#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6246#define DMA_HIFCR_CFEIF7_Pos (22U)
6247#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6248#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6249#define DMA_HIFCR_CTCIF6_Pos (21U)
6250#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6251#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6252#define DMA_HIFCR_CHTIF6_Pos (20U)
6253#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6254#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6255#define DMA_HIFCR_CTEIF6_Pos (19U)
6256#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6257#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6258#define DMA_HIFCR_CDMEIF6_Pos (18U)
6259#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6260#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6261#define DMA_HIFCR_CFEIF6_Pos (16U)
6262#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6263#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6264#define DMA_HIFCR_CTCIF5_Pos (11U)
6265#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6266#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6267#define DMA_HIFCR_CHTIF5_Pos (10U)
6268#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6269#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6270#define DMA_HIFCR_CTEIF5_Pos (9U)
6271#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6272#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6273#define DMA_HIFCR_CDMEIF5_Pos (8U)
6274#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6275#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6276#define DMA_HIFCR_CFEIF5_Pos (6U)
6277#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6278#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6279#define DMA_HIFCR_CTCIF4_Pos (5U)
6280#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6281#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6282#define DMA_HIFCR_CHTIF4_Pos (4U)
6283#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6284#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6285#define DMA_HIFCR_CTEIF4_Pos (3U)
6286#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6287#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6288#define DMA_HIFCR_CDMEIF4_Pos (2U)
6289#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6290#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6291#define DMA_HIFCR_CFEIF4_Pos (0U)
6292#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6293#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6294
6295/****************** Bit definition for DMA_SxPAR register ********************/
6296#define DMA_SxPAR_PA_Pos (0U)
6297#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6298#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6299
6300/****************** Bit definition for DMA_SxM0AR register ********************/
6301#define DMA_SxM0AR_M0A_Pos (0U)
6302#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6303#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6304
6305/****************** Bit definition for DMA_SxM1AR register ********************/
6306#define DMA_SxM1AR_M1A_Pos (0U)
6307#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6308#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6309
6310
6311/******************************************************************************/
6312/* */
6313/* External Interrupt/Event Controller */
6314/* */
6315/******************************************************************************/
6316/******************* Bit definition for EXTI_IMR register *******************/
6317#define EXTI_IMR_MR0_Pos (0U)
6318#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6319#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6320#define EXTI_IMR_MR1_Pos (1U)
6321#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6322#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6323#define EXTI_IMR_MR2_Pos (2U)
6324#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6325#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6326#define EXTI_IMR_MR3_Pos (3U)
6327#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6328#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6329#define EXTI_IMR_MR4_Pos (4U)
6330#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6331#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6332#define EXTI_IMR_MR5_Pos (5U)
6333#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6334#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6335#define EXTI_IMR_MR6_Pos (6U)
6336#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6337#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6338#define EXTI_IMR_MR7_Pos (7U)
6339#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6340#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6341#define EXTI_IMR_MR8_Pos (8U)
6342#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6343#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6344#define EXTI_IMR_MR9_Pos (9U)
6345#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6346#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6347#define EXTI_IMR_MR10_Pos (10U)
6348#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6349#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6350#define EXTI_IMR_MR11_Pos (11U)
6351#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6352#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6353#define EXTI_IMR_MR12_Pos (12U)
6354#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6355#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6356#define EXTI_IMR_MR13_Pos (13U)
6357#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6358#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6359#define EXTI_IMR_MR14_Pos (14U)
6360#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6361#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6362#define EXTI_IMR_MR15_Pos (15U)
6363#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6364#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6365#define EXTI_IMR_MR16_Pos (16U)
6366#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6367#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6368#define EXTI_IMR_MR17_Pos (17U)
6369#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6370#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6371#define EXTI_IMR_MR18_Pos (18U)
6372#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6373#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6374#define EXTI_IMR_MR19_Pos (19U)
6375#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6376#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6377#define EXTI_IMR_MR20_Pos (20U)
6378#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6379#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6380#define EXTI_IMR_MR21_Pos (21U)
6381#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6382#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6383#define EXTI_IMR_MR22_Pos (22U)
6384#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6385#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6386#define EXTI_IMR_MR23_Pos (23U)
6387#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
6388#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
6389
6390/* Reference Defines */
6391#define EXTI_IMR_IM0 EXTI_IMR_MR0
6392#define EXTI_IMR_IM1 EXTI_IMR_MR1
6393#define EXTI_IMR_IM2 EXTI_IMR_MR2
6394#define EXTI_IMR_IM3 EXTI_IMR_MR3
6395#define EXTI_IMR_IM4 EXTI_IMR_MR4
6396#define EXTI_IMR_IM5 EXTI_IMR_MR5
6397#define EXTI_IMR_IM6 EXTI_IMR_MR6
6398#define EXTI_IMR_IM7 EXTI_IMR_MR7
6399#define EXTI_IMR_IM8 EXTI_IMR_MR8
6400#define EXTI_IMR_IM9 EXTI_IMR_MR9
6401#define EXTI_IMR_IM10 EXTI_IMR_MR10
6402#define EXTI_IMR_IM11 EXTI_IMR_MR11
6403#define EXTI_IMR_IM12 EXTI_IMR_MR12
6404#define EXTI_IMR_IM13 EXTI_IMR_MR13
6405#define EXTI_IMR_IM14 EXTI_IMR_MR14
6406#define EXTI_IMR_IM15 EXTI_IMR_MR15
6407#define EXTI_IMR_IM16 EXTI_IMR_MR16
6408#define EXTI_IMR_IM17 EXTI_IMR_MR17
6409#define EXTI_IMR_IM18 EXTI_IMR_MR18
6410#define EXTI_IMR_IM19 EXTI_IMR_MR19
6411#define EXTI_IMR_IM20 EXTI_IMR_MR20
6412#define EXTI_IMR_IM21 EXTI_IMR_MR21
6413#define EXTI_IMR_IM22 EXTI_IMR_MR22
6414#define EXTI_IMR_IM23 EXTI_IMR_MR23
6415#define EXTI_IMR_IM_Pos (0U)
6416#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos)
6417#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6418
6419/******************* Bit definition for EXTI_EMR register *******************/
6420#define EXTI_EMR_MR0_Pos (0U)
6421#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6422#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6423#define EXTI_EMR_MR1_Pos (1U)
6424#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6425#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6426#define EXTI_EMR_MR2_Pos (2U)
6427#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6428#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6429#define EXTI_EMR_MR3_Pos (3U)
6430#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6431#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6432#define EXTI_EMR_MR4_Pos (4U)
6433#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6434#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6435#define EXTI_EMR_MR5_Pos (5U)
6436#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6437#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6438#define EXTI_EMR_MR6_Pos (6U)
6439#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6440#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6441#define EXTI_EMR_MR7_Pos (7U)
6442#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6443#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6444#define EXTI_EMR_MR8_Pos (8U)
6445#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6446#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6447#define EXTI_EMR_MR9_Pos (9U)
6448#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6449#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6450#define EXTI_EMR_MR10_Pos (10U)
6451#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6452#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6453#define EXTI_EMR_MR11_Pos (11U)
6454#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6455#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6456#define EXTI_EMR_MR12_Pos (12U)
6457#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6458#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6459#define EXTI_EMR_MR13_Pos (13U)
6460#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6461#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6462#define EXTI_EMR_MR14_Pos (14U)
6463#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6464#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6465#define EXTI_EMR_MR15_Pos (15U)
6466#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6467#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6468#define EXTI_EMR_MR16_Pos (16U)
6469#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6470#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6471#define EXTI_EMR_MR17_Pos (17U)
6472#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6473#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6474#define EXTI_EMR_MR18_Pos (18U)
6475#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6476#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6477#define EXTI_EMR_MR19_Pos (19U)
6478#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6479#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6480#define EXTI_EMR_MR20_Pos (20U)
6481#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6482#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6483#define EXTI_EMR_MR21_Pos (21U)
6484#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6485#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6486#define EXTI_EMR_MR22_Pos (22U)
6487#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6488#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6489#define EXTI_EMR_MR23_Pos (23U)
6490#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
6491#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
6492
6493/* Reference Defines */
6494#define EXTI_EMR_EM0 EXTI_EMR_MR0
6495#define EXTI_EMR_EM1 EXTI_EMR_MR1
6496#define EXTI_EMR_EM2 EXTI_EMR_MR2
6497#define EXTI_EMR_EM3 EXTI_EMR_MR3
6498#define EXTI_EMR_EM4 EXTI_EMR_MR4
6499#define EXTI_EMR_EM5 EXTI_EMR_MR5
6500#define EXTI_EMR_EM6 EXTI_EMR_MR6
6501#define EXTI_EMR_EM7 EXTI_EMR_MR7
6502#define EXTI_EMR_EM8 EXTI_EMR_MR8
6503#define EXTI_EMR_EM9 EXTI_EMR_MR9
6504#define EXTI_EMR_EM10 EXTI_EMR_MR10
6505#define EXTI_EMR_EM11 EXTI_EMR_MR11
6506#define EXTI_EMR_EM12 EXTI_EMR_MR12
6507#define EXTI_EMR_EM13 EXTI_EMR_MR13
6508#define EXTI_EMR_EM14 EXTI_EMR_MR14
6509#define EXTI_EMR_EM15 EXTI_EMR_MR15
6510#define EXTI_EMR_EM16 EXTI_EMR_MR16
6511#define EXTI_EMR_EM17 EXTI_EMR_MR17
6512#define EXTI_EMR_EM18 EXTI_EMR_MR18
6513#define EXTI_EMR_EM19 EXTI_EMR_MR19
6514#define EXTI_EMR_EM20 EXTI_EMR_MR20
6515#define EXTI_EMR_EM21 EXTI_EMR_MR21
6516#define EXTI_EMR_EM22 EXTI_EMR_MR22
6517#define EXTI_EMR_EM23 EXTI_EMR_MR23
6518
6519/****************** Bit definition for EXTI_RTSR register *******************/
6520#define EXTI_RTSR_TR0_Pos (0U)
6521#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6522#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6523#define EXTI_RTSR_TR1_Pos (1U)
6524#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6525#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6526#define EXTI_RTSR_TR2_Pos (2U)
6527#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6528#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6529#define EXTI_RTSR_TR3_Pos (3U)
6530#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6531#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6532#define EXTI_RTSR_TR4_Pos (4U)
6533#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6534#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6535#define EXTI_RTSR_TR5_Pos (5U)
6536#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6537#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6538#define EXTI_RTSR_TR6_Pos (6U)
6539#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6540#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6541#define EXTI_RTSR_TR7_Pos (7U)
6542#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6543#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6544#define EXTI_RTSR_TR8_Pos (8U)
6545#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6546#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6547#define EXTI_RTSR_TR9_Pos (9U)
6548#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6549#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6550#define EXTI_RTSR_TR10_Pos (10U)
6551#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6552#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6553#define EXTI_RTSR_TR11_Pos (11U)
6554#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6555#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6556#define EXTI_RTSR_TR12_Pos (12U)
6557#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6558#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6559#define EXTI_RTSR_TR13_Pos (13U)
6560#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6561#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6562#define EXTI_RTSR_TR14_Pos (14U)
6563#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6564#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6565#define EXTI_RTSR_TR15_Pos (15U)
6566#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6567#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6568#define EXTI_RTSR_TR16_Pos (16U)
6569#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6570#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6571#define EXTI_RTSR_TR17_Pos (17U)
6572#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6573#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6574#define EXTI_RTSR_TR18_Pos (18U)
6575#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6576#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6577#define EXTI_RTSR_TR19_Pos (19U)
6578#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6579#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6580#define EXTI_RTSR_TR20_Pos (20U)
6581#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6582#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6583#define EXTI_RTSR_TR21_Pos (21U)
6584#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6585#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6586#define EXTI_RTSR_TR22_Pos (22U)
6587#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6588#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6589#define EXTI_RTSR_TR23_Pos (23U)
6590#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
6591#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
6592
6593/****************** Bit definition for EXTI_FTSR register *******************/
6594#define EXTI_FTSR_TR0_Pos (0U)
6595#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6596#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6597#define EXTI_FTSR_TR1_Pos (1U)
6598#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6599#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6600#define EXTI_FTSR_TR2_Pos (2U)
6601#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6602#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6603#define EXTI_FTSR_TR3_Pos (3U)
6604#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6605#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6606#define EXTI_FTSR_TR4_Pos (4U)
6607#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6608#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6609#define EXTI_FTSR_TR5_Pos (5U)
6610#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6611#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6612#define EXTI_FTSR_TR6_Pos (6U)
6613#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6614#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6615#define EXTI_FTSR_TR7_Pos (7U)
6616#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6617#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6618#define EXTI_FTSR_TR8_Pos (8U)
6619#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6620#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6621#define EXTI_FTSR_TR9_Pos (9U)
6622#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6623#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6624#define EXTI_FTSR_TR10_Pos (10U)
6625#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6626#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6627#define EXTI_FTSR_TR11_Pos (11U)
6628#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6629#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6630#define EXTI_FTSR_TR12_Pos (12U)
6631#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6632#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6633#define EXTI_FTSR_TR13_Pos (13U)
6634#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6635#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6636#define EXTI_FTSR_TR14_Pos (14U)
6637#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6638#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6639#define EXTI_FTSR_TR15_Pos (15U)
6640#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6641#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6642#define EXTI_FTSR_TR16_Pos (16U)
6643#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6644#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6645#define EXTI_FTSR_TR17_Pos (17U)
6646#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6647#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6648#define EXTI_FTSR_TR18_Pos (18U)
6649#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6650#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6651#define EXTI_FTSR_TR19_Pos (19U)
6652#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6653#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6654#define EXTI_FTSR_TR20_Pos (20U)
6655#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6656#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6657#define EXTI_FTSR_TR21_Pos (21U)
6658#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6659#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6660#define EXTI_FTSR_TR22_Pos (22U)
6661#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6662#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6663#define EXTI_FTSR_TR23_Pos (23U)
6664#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
6665#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
6666
6667/****************** Bit definition for EXTI_SWIER register ******************/
6668#define EXTI_SWIER_SWIER0_Pos (0U)
6669#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6670#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6671#define EXTI_SWIER_SWIER1_Pos (1U)
6672#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6673#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6674#define EXTI_SWIER_SWIER2_Pos (2U)
6675#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6676#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6677#define EXTI_SWIER_SWIER3_Pos (3U)
6678#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6679#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6680#define EXTI_SWIER_SWIER4_Pos (4U)
6681#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6682#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6683#define EXTI_SWIER_SWIER5_Pos (5U)
6684#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6685#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6686#define EXTI_SWIER_SWIER6_Pos (6U)
6687#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6688#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6689#define EXTI_SWIER_SWIER7_Pos (7U)
6690#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6691#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6692#define EXTI_SWIER_SWIER8_Pos (8U)
6693#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6694#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6695#define EXTI_SWIER_SWIER9_Pos (9U)
6696#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6697#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6698#define EXTI_SWIER_SWIER10_Pos (10U)
6699#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6700#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6701#define EXTI_SWIER_SWIER11_Pos (11U)
6702#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6703#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6704#define EXTI_SWIER_SWIER12_Pos (12U)
6705#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6706#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6707#define EXTI_SWIER_SWIER13_Pos (13U)
6708#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6709#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6710#define EXTI_SWIER_SWIER14_Pos (14U)
6711#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6712#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6713#define EXTI_SWIER_SWIER15_Pos (15U)
6714#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6715#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6716#define EXTI_SWIER_SWIER16_Pos (16U)
6717#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6718#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6719#define EXTI_SWIER_SWIER17_Pos (17U)
6720#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6721#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6722#define EXTI_SWIER_SWIER18_Pos (18U)
6723#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6724#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6725#define EXTI_SWIER_SWIER19_Pos (19U)
6726#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6727#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6728#define EXTI_SWIER_SWIER20_Pos (20U)
6729#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6730#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6731#define EXTI_SWIER_SWIER21_Pos (21U)
6732#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6733#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6734#define EXTI_SWIER_SWIER22_Pos (22U)
6735#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6736#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6737#define EXTI_SWIER_SWIER23_Pos (23U)
6738#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
6739#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
6740
6741/******************* Bit definition for EXTI_PR register ********************/
6742#define EXTI_PR_PR0_Pos (0U)
6743#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6744#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6745#define EXTI_PR_PR1_Pos (1U)
6746#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6747#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6748#define EXTI_PR_PR2_Pos (2U)
6749#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6750#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6751#define EXTI_PR_PR3_Pos (3U)
6752#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6753#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6754#define EXTI_PR_PR4_Pos (4U)
6755#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6756#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6757#define EXTI_PR_PR5_Pos (5U)
6758#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6759#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6760#define EXTI_PR_PR6_Pos (6U)
6761#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6762#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6763#define EXTI_PR_PR7_Pos (7U)
6764#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6765#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6766#define EXTI_PR_PR8_Pos (8U)
6767#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6768#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6769#define EXTI_PR_PR9_Pos (9U)
6770#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6771#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6772#define EXTI_PR_PR10_Pos (10U)
6773#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6774#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6775#define EXTI_PR_PR11_Pos (11U)
6776#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6777#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6778#define EXTI_PR_PR12_Pos (12U)
6779#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6780#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6781#define EXTI_PR_PR13_Pos (13U)
6782#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6783#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6784#define EXTI_PR_PR14_Pos (14U)
6785#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6786#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6787#define EXTI_PR_PR15_Pos (15U)
6788#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6789#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6790#define EXTI_PR_PR16_Pos (16U)
6791#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6792#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6793#define EXTI_PR_PR17_Pos (17U)
6794#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6795#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6796#define EXTI_PR_PR18_Pos (18U)
6797#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6798#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6799#define EXTI_PR_PR19_Pos (19U)
6800#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6801#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6802#define EXTI_PR_PR20_Pos (20U)
6803#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6804#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6805#define EXTI_PR_PR21_Pos (21U)
6806#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6807#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6808#define EXTI_PR_PR22_Pos (22U)
6809#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6810#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6811#define EXTI_PR_PR23_Pos (23U)
6812#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
6813#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
6814
6815/******************************************************************************/
6816/* */
6817/* FLASH */
6818/* */
6819/******************************************************************************/
6820/******************* Bits definition for FLASH_ACR register *****************/
6821#define FLASH_ACR_LATENCY_Pos (0U)
6822#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6823#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6824#define FLASH_ACR_LATENCY_0WS 0x00000000U
6825#define FLASH_ACR_LATENCY_1WS 0x00000001U
6826#define FLASH_ACR_LATENCY_2WS 0x00000002U
6827#define FLASH_ACR_LATENCY_3WS 0x00000003U
6828#define FLASH_ACR_LATENCY_4WS 0x00000004U
6829#define FLASH_ACR_LATENCY_5WS 0x00000005U
6830#define FLASH_ACR_LATENCY_6WS 0x00000006U
6831#define FLASH_ACR_LATENCY_7WS 0x00000007U
6832
6833
6834#define FLASH_ACR_PRFTEN_Pos (8U)
6835#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6836#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6837#define FLASH_ACR_ICEN_Pos (9U)
6838#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6839#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6840#define FLASH_ACR_DCEN_Pos (10U)
6841#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6842#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6843#define FLASH_ACR_ICRST_Pos (11U)
6844#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6845#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6846#define FLASH_ACR_DCRST_Pos (12U)
6847#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6848#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6849
6850/******************* Bits definition for FLASH_SR register ******************/
6851#define FLASH_SR_EOP_Pos (0U)
6852#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6853#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6854#define FLASH_SR_OPERR_Pos (1U)
6855#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
6856#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6857#define FLASH_SR_WRPERR_Pos (4U)
6858#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6859#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6860#define FLASH_SR_PGAERR_Pos (5U)
6861#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6862#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6863#define FLASH_SR_PGPERR_Pos (6U)
6864#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6865#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6866#define FLASH_SR_PGSERR_Pos (7U)
6867#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6868#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6869#define FLASH_SR_RDERR_Pos (8U)
6870#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6871#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6872#define FLASH_SR_BSY_Pos (16U)
6873#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6874#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6875
6876/******************* Bits definition for FLASH_CR register ******************/
6877#define FLASH_CR_PG_Pos (0U)
6878#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6879#define FLASH_CR_PG FLASH_CR_PG_Msk
6880#define FLASH_CR_SER_Pos (1U)
6881#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6882#define FLASH_CR_SER FLASH_CR_SER_Msk
6883#define FLASH_CR_MER_Pos (2U)
6884#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6885#define FLASH_CR_MER FLASH_CR_MER_Msk
6886#define FLASH_CR_SNB_Pos (3U)
6887#define FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos)
6888#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6889#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6890#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6891#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6892#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6893#define FLASH_CR_PSIZE_Pos (8U)
6894#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6895#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6896#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6897#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6898#define FLASH_CR_STRT_Pos (16U)
6899#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6900#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6901#define FLASH_CR_EOPIE_Pos (24U)
6902#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6903#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6904#define FLASH_CR_ERRIE_Pos (25U)
6905#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6906#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6907#define FLASH_CR_LOCK_Pos (31U)
6908#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6909#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6910
6911/******************* Bits definition for FLASH_OPTCR register ***************/
6912#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6913#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6914#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6915#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6916#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6917#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6918
6919#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6920#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6921#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6922#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6923#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6924#define FLASH_OPTCR_WDG_SW_Pos (5U)
6925#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6926#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6927#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6928#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6929#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6930#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6931#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6932#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6933#define FLASH_OPTCR_RDP_Pos (8U)
6934#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6935#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6936#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6937#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6938#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6939#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6940#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6941#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6942#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6943#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6944#define FLASH_OPTCR_nWRP_Pos (16U)
6945#define FLASH_OPTCR_nWRP_Msk (0x7FFFUL << FLASH_OPTCR_nWRP_Pos)
6946#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6947#define FLASH_OPTCR_nWRP_0 0x00010000U
6948#define FLASH_OPTCR_nWRP_1 0x00020000U
6949#define FLASH_OPTCR_nWRP_2 0x00040000U
6950#define FLASH_OPTCR_nWRP_3 0x00080000U
6951#define FLASH_OPTCR_nWRP_4 0x00100000U
6952#define FLASH_OPTCR_nWRP_5 0x00200000U
6953#define FLASH_OPTCR_nWRP_6 0x00400000U
6954#define FLASH_OPTCR_nWRP_7 0x00800000U
6955#define FLASH_OPTCR_nWRP_8 0x01000000U
6956#define FLASH_OPTCR_nWRP_9 0x02000000U
6957#define FLASH_OPTCR_nWRP_10 0x04000000U
6958#define FLASH_OPTCR_nWRP_11 0x08000000U
6959#define FLASH_OPTCR_nWRP_12 0x10000000U
6960#define FLASH_OPTCR_nWRP_13 0x20000000U
6961#define FLASH_OPTCR_nWRP_14 0x40000000U
6962#define FLASH_OPTCR_nWRP_15 0x40000000U
6963
6964/****************** Bits definition for FLASH_OPTCR1 register ***************/
6965#define FLASH_OPTCR1_nWRP_Pos (16U)
6966#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
6967#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6968#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
6969#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
6970#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
6971#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
6972#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
6973#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
6974#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
6975#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
6976#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
6977#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
6978#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
6979#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
6980/* Legacy defines */
6981#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
6982#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
6983#define FLASH_SR_SOP FLASH_SR_OPERR
6984#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6985#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6986#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6987#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6988#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6989#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6990
6991/******************************************************************************/
6992/* */
6993/* Flexible Static Memory Controller */
6994/* */
6995/******************************************************************************/
6996/****************** Bit definition for FSMC_BCR1 register *******************/
6997#define FSMC_BCR1_MBKEN_Pos (0U)
6998#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6999#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
7000#define FSMC_BCR1_MUXEN_Pos (1U)
7001#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
7002#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
7003
7004#define FSMC_BCR1_MTYP_Pos (2U)
7005#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
7006#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
7007#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
7008#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
7009
7010#define FSMC_BCR1_MWID_Pos (4U)
7011#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
7012#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
7013#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
7014#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
7015
7016#define FSMC_BCR1_FACCEN_Pos (6U)
7017#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
7018#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
7019#define FSMC_BCR1_BURSTEN_Pos (8U)
7020#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
7021#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
7022#define FSMC_BCR1_WAITPOL_Pos (9U)
7023#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
7024#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
7025#define FSMC_BCR1_WAITCFG_Pos (11U)
7026#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
7027#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
7028#define FSMC_BCR1_WREN_Pos (12U)
7029#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
7030#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
7031#define FSMC_BCR1_WAITEN_Pos (13U)
7032#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
7033#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
7034#define FSMC_BCR1_EXTMOD_Pos (14U)
7035#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
7036#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
7037#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
7038#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
7039#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
7040#define FSMC_BCR1_CPSIZE_Pos (16U)
7041#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
7042#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
7043#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
7044#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
7045#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
7046#define FSMC_BCR1_CBURSTRW_Pos (19U)
7047#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
7048#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
7049#define FSMC_BCR1_CCLKEN_Pos (20U)
7050#define FSMC_BCR1_CCLKEN_Msk (0x1UL << FSMC_BCR1_CCLKEN_Pos)
7051#define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk
7052#define FSMC_BCR1_WFDIS_Pos (21U)
7053#define FSMC_BCR1_WFDIS_Msk (0x1UL << FSMC_BCR1_WFDIS_Pos)
7054#define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk
7055
7056/****************** Bit definition for FSMC_BCR2 register *******************/
7057#define FSMC_BCR2_MBKEN_Pos (0U)
7058#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
7059#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
7060#define FSMC_BCR2_MUXEN_Pos (1U)
7061#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
7062#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
7063
7064#define FSMC_BCR2_MTYP_Pos (2U)
7065#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
7066#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
7067#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
7068#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
7069
7070#define FSMC_BCR2_MWID_Pos (4U)
7071#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
7072#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
7073#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
7074#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
7075
7076#define FSMC_BCR2_FACCEN_Pos (6U)
7077#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
7078#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
7079#define FSMC_BCR2_BURSTEN_Pos (8U)
7080#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
7081#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
7082#define FSMC_BCR2_WAITPOL_Pos (9U)
7083#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
7084#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
7085#define FSMC_BCR2_WAITCFG_Pos (11U)
7086#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
7087#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
7088#define FSMC_BCR2_WREN_Pos (12U)
7089#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
7090#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
7091#define FSMC_BCR2_WAITEN_Pos (13U)
7092#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
7093#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
7094#define FSMC_BCR2_EXTMOD_Pos (14U)
7095#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
7096#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
7097#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
7098#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
7099#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
7100#define FSMC_BCR2_CPSIZE_Pos (16U)
7101#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
7102#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
7103#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
7104#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
7105#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
7106#define FSMC_BCR2_CBURSTRW_Pos (19U)
7107#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
7108#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
7109
7110/****************** Bit definition for FSMC_BCR3 register *******************/
7111#define FSMC_BCR3_MBKEN_Pos (0U)
7112#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
7113#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
7114#define FSMC_BCR3_MUXEN_Pos (1U)
7115#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
7116#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
7117
7118#define FSMC_BCR3_MTYP_Pos (2U)
7119#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
7120#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
7121#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
7122#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
7123
7124#define FSMC_BCR3_MWID_Pos (4U)
7125#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
7126#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
7127#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
7128#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
7129
7130#define FSMC_BCR3_FACCEN_Pos (6U)
7131#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
7132#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
7133#define FSMC_BCR3_BURSTEN_Pos (8U)
7134#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
7135#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
7136#define FSMC_BCR3_WAITPOL_Pos (9U)
7137#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
7138#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
7139#define FSMC_BCR3_WAITCFG_Pos (11U)
7140#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
7141#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
7142#define FSMC_BCR3_WREN_Pos (12U)
7143#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
7144#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
7145#define FSMC_BCR3_WAITEN_Pos (13U)
7146#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
7147#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
7148#define FSMC_BCR3_EXTMOD_Pos (14U)
7149#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
7150#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
7151#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
7152#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
7153#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
7154#define FSMC_BCR3_CPSIZE_Pos (16U)
7155#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
7156#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
7157#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
7158#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
7159#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
7160#define FSMC_BCR3_CBURSTRW_Pos (19U)
7161#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
7162#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
7163
7164/****************** Bit definition for FSMC_BCR4 register *******************/
7165#define FSMC_BCR4_MBKEN_Pos (0U)
7166#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
7167#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
7168#define FSMC_BCR4_MUXEN_Pos (1U)
7169#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
7170#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
7171
7172#define FSMC_BCR4_MTYP_Pos (2U)
7173#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
7174#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
7175#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
7176#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
7177
7178#define FSMC_BCR4_MWID_Pos (4U)
7179#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
7180#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
7181#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
7182#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
7183
7184#define FSMC_BCR4_FACCEN_Pos (6U)
7185#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
7186#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
7187#define FSMC_BCR4_BURSTEN_Pos (8U)
7188#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
7189#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
7190#define FSMC_BCR4_WAITPOL_Pos (9U)
7191#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
7192#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
7193#define FSMC_BCR4_WAITCFG_Pos (11U)
7194#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
7195#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
7196#define FSMC_BCR4_WREN_Pos (12U)
7197#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
7198#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
7199#define FSMC_BCR4_WAITEN_Pos (13U)
7200#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
7201#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
7202#define FSMC_BCR4_EXTMOD_Pos (14U)
7203#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
7204#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
7205#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7206#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
7207#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
7208#define FSMC_BCR4_CPSIZE_Pos (16U)
7209#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
7210#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
7211#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
7212#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
7213#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
7214#define FSMC_BCR4_CBURSTRW_Pos (19U)
7215#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
7216#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
7217
7218/****************** Bit definition for FSMC_BTR1 register ******************/
7219#define FSMC_BTR1_ADDSET_Pos (0U)
7220#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
7221#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
7222#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
7223#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
7224#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
7225#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
7226
7227#define FSMC_BTR1_ADDHLD_Pos (4U)
7228#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
7229#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
7230#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
7231#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
7232#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
7233#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
7234
7235#define FSMC_BTR1_DATAST_Pos (8U)
7236#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
7237#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
7238#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
7239#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
7240#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
7241#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
7242#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
7243#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
7244#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
7245#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
7246
7247#define FSMC_BTR1_BUSTURN_Pos (16U)
7248#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
7249#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
7250#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
7251#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
7252#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
7253#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
7254
7255#define FSMC_BTR1_CLKDIV_Pos (20U)
7256#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
7257#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
7258#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
7259#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
7260#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
7261#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
7262
7263#define FSMC_BTR1_DATLAT_Pos (24U)
7264#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
7265#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
7266#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
7267#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
7268#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
7269#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
7270
7271#define FSMC_BTR1_ACCMOD_Pos (28U)
7272#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
7273#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
7274#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
7275#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
7276
7277/****************** Bit definition for FSMC_BTR2 register *******************/
7278#define FSMC_BTR2_ADDSET_Pos (0U)
7279#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
7280#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
7281#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
7282#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
7283#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
7284#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
7285
7286#define FSMC_BTR2_ADDHLD_Pos (4U)
7287#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
7288#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
7289#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
7290#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
7291#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
7292#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
7293
7294#define FSMC_BTR2_DATAST_Pos (8U)
7295#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
7296#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
7297#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
7298#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
7299#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
7300#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
7301#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
7302#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
7303#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
7304#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
7305
7306#define FSMC_BTR2_BUSTURN_Pos (16U)
7307#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
7308#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
7309#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
7310#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
7311#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
7312#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
7313
7314#define FSMC_BTR2_CLKDIV_Pos (20U)
7315#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
7316#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
7317#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
7318#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
7319#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
7320#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
7321
7322#define FSMC_BTR2_DATLAT_Pos (24U)
7323#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7324#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7325#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7326#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7327#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7328#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7329
7330#define FSMC_BTR2_ACCMOD_Pos (28U)
7331#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7332#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7333#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7334#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7335
7336/******************* Bit definition for FSMC_BTR3 register *******************/
7337#define FSMC_BTR3_ADDSET_Pos (0U)
7338#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7339#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7340#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7341#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7342#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7343#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7344
7345#define FSMC_BTR3_ADDHLD_Pos (4U)
7346#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7347#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7348#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7349#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7350#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7351#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7352
7353#define FSMC_BTR3_DATAST_Pos (8U)
7354#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7355#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7356#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7357#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7358#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7359#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7360#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7361#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7362#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7363#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7364
7365#define FSMC_BTR3_BUSTURN_Pos (16U)
7366#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7367#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7368#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7369#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7370#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7371#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7372
7373#define FSMC_BTR3_CLKDIV_Pos (20U)
7374#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7375#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7376#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7377#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7378#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7379#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7380
7381#define FSMC_BTR3_DATLAT_Pos (24U)
7382#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7383#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7384#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7385#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7386#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7387#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7388
7389#define FSMC_BTR3_ACCMOD_Pos (28U)
7390#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7391#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7392#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7393#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7394
7395/****************** Bit definition for FSMC_BTR4 register *******************/
7396#define FSMC_BTR4_ADDSET_Pos (0U)
7397#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7398#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7399#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7400#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7401#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7402#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7403
7404#define FSMC_BTR4_ADDHLD_Pos (4U)
7405#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7406#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7407#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7408#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7409#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7410#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7411
7412#define FSMC_BTR4_DATAST_Pos (8U)
7413#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7414#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7415#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7416#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7417#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7418#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7419#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7420#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7421#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7422#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7423
7424#define FSMC_BTR4_BUSTURN_Pos (16U)
7425#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7426#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7427#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7428#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7429#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7430#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7431
7432#define FSMC_BTR4_CLKDIV_Pos (20U)
7433#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7434#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7435#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7436#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7437#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7438#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7439
7440#define FSMC_BTR4_DATLAT_Pos (24U)
7441#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7442#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7443#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7444#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7445#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7446#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7447
7448#define FSMC_BTR4_ACCMOD_Pos (28U)
7449#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7450#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7451#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7452#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7453
7454/****************** Bit definition for FSMC_BWTR1 register ******************/
7455#define FSMC_BWTR1_ADDSET_Pos (0U)
7456#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7457#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7458#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7459#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7460#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7461#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7462
7463#define FSMC_BWTR1_ADDHLD_Pos (4U)
7464#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7465#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7466#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7467#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7468#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7469#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7470
7471#define FSMC_BWTR1_DATAST_Pos (8U)
7472#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7473#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7474#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7475#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7476#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7477#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7478#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7479#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7480#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7481#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7482
7483#define FSMC_BWTR1_BUSTURN_Pos (16U)
7484#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7485#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7486#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7487#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7488#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7489#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7490
7491#define FSMC_BWTR1_ACCMOD_Pos (28U)
7492#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7493#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7494#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7495#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7496
7497/****************** Bit definition for FSMC_BWTR2 register ******************/
7498#define FSMC_BWTR2_ADDSET_Pos (0U)
7499#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7500#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7501#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7502#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7503#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7504#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7505
7506#define FSMC_BWTR2_ADDHLD_Pos (4U)
7507#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7508#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7509#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7510#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7511#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7512#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7513
7514#define FSMC_BWTR2_DATAST_Pos (8U)
7515#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7516#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7517#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7518#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7519#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7520#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7521#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7522#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7523#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7524#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7525
7526#define FSMC_BWTR2_BUSTURN_Pos (16U)
7527#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7528#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7529#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7530#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7531#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7532#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7533
7534#define FSMC_BWTR2_ACCMOD_Pos (28U)
7535#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7536#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7537#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7538#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7539
7540/****************** Bit definition for FSMC_BWTR3 register ******************/
7541#define FSMC_BWTR3_ADDSET_Pos (0U)
7542#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7543#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7544#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7545#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7546#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7547#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7548
7549#define FSMC_BWTR3_ADDHLD_Pos (4U)
7550#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7551#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7552#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7553#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7554#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7555#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7556
7557#define FSMC_BWTR3_DATAST_Pos (8U)
7558#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7559#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7560#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7561#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7562#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7563#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7564#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7565#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7566#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7567#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7568
7569#define FSMC_BWTR3_BUSTURN_Pos (16U)
7570#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7571#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7572#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7573#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7574#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7575#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7576
7577#define FSMC_BWTR3_ACCMOD_Pos (28U)
7578#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7579#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7580#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7581#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7582
7583/****************** Bit definition for FSMC_BWTR4 register ******************/
7584#define FSMC_BWTR4_ADDSET_Pos (0U)
7585#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7586#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7587#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7588#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7589#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7590#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7591
7592#define FSMC_BWTR4_ADDHLD_Pos (4U)
7593#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7594#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7595#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7596#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7597#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7598#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7599
7600#define FSMC_BWTR4_DATAST_Pos (8U)
7601#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7602#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7603#define FSMC_BWTR4_DATAST_0 0x00000100U
7604#define FSMC_BWTR4_DATAST_1 0x00000200U
7605#define FSMC_BWTR4_DATAST_2 0x00000400U
7606#define FSMC_BWTR4_DATAST_3 0x00000800U
7607#define FSMC_BWTR4_DATAST_4 0x00001000U
7608#define FSMC_BWTR4_DATAST_5 0x00002000U
7609#define FSMC_BWTR4_DATAST_6 0x00004000U
7610#define FSMC_BWTR4_DATAST_7 0x00008000U
7611
7612#define FSMC_BWTR4_BUSTURN_Pos (16U)
7613#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7614#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7615#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7616#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7617#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7618#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7619
7620#define FSMC_BWTR4_ACCMOD_Pos (28U)
7621#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7622#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7623#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7624#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7625
7626/******************************************************************************/
7627/* */
7628/* General Purpose I/O */
7629/* */
7630/******************************************************************************/
7631/****************** Bits definition for GPIO_MODER register *****************/
7632#define GPIO_MODER_MODER0_Pos (0U)
7633#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
7634#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7635#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
7636#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
7637#define GPIO_MODER_MODER1_Pos (2U)
7638#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
7639#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7640#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
7641#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
7642#define GPIO_MODER_MODER2_Pos (4U)
7643#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
7644#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7645#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
7646#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
7647#define GPIO_MODER_MODER3_Pos (6U)
7648#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
7649#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7650#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
7651#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
7652#define GPIO_MODER_MODER4_Pos (8U)
7653#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
7654#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7655#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
7656#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
7657#define GPIO_MODER_MODER5_Pos (10U)
7658#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
7659#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7660#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
7661#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
7662#define GPIO_MODER_MODER6_Pos (12U)
7663#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
7664#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7665#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
7666#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
7667#define GPIO_MODER_MODER7_Pos (14U)
7668#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
7669#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7670#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
7671#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
7672#define GPIO_MODER_MODER8_Pos (16U)
7673#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
7674#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7675#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
7676#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
7677#define GPIO_MODER_MODER9_Pos (18U)
7678#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
7679#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7680#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
7681#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
7682#define GPIO_MODER_MODER10_Pos (20U)
7683#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
7684#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7685#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
7686#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
7687#define GPIO_MODER_MODER11_Pos (22U)
7688#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
7689#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7690#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
7691#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
7692#define GPIO_MODER_MODER12_Pos (24U)
7693#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
7694#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7695#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
7696#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
7697#define GPIO_MODER_MODER13_Pos (26U)
7698#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
7699#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7700#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
7701#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
7702#define GPIO_MODER_MODER14_Pos (28U)
7703#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
7704#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7705#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
7706#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
7707#define GPIO_MODER_MODER15_Pos (30U)
7708#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
7709#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7710#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
7711#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
7712
7713
7714/****************** Bits definition for GPIO_OTYPER register ****************/
7715#define GPIO_OTYPER_OT0_Pos (0U)
7716#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7717#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7718#define GPIO_OTYPER_OT1_Pos (1U)
7719#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7720#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7721#define GPIO_OTYPER_OT2_Pos (2U)
7722#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7723#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7724#define GPIO_OTYPER_OT3_Pos (3U)
7725#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7726#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7727#define GPIO_OTYPER_OT4_Pos (4U)
7728#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7729#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7730#define GPIO_OTYPER_OT5_Pos (5U)
7731#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7732#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7733#define GPIO_OTYPER_OT6_Pos (6U)
7734#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7735#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7736#define GPIO_OTYPER_OT7_Pos (7U)
7737#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7738#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7739#define GPIO_OTYPER_OT8_Pos (8U)
7740#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7741#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7742#define GPIO_OTYPER_OT9_Pos (9U)
7743#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7744#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7745#define GPIO_OTYPER_OT10_Pos (10U)
7746#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7747#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7748#define GPIO_OTYPER_OT11_Pos (11U)
7749#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7750#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7751#define GPIO_OTYPER_OT12_Pos (12U)
7752#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7753#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7754#define GPIO_OTYPER_OT13_Pos (13U)
7755#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7756#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7757#define GPIO_OTYPER_OT14_Pos (14U)
7758#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7759#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7760#define GPIO_OTYPER_OT15_Pos (15U)
7761#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7762#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7763
7764/* Legacy defines */
7765#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7766#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7767#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7768#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7769#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7770#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7771#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7772#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7773#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7774#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7775#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7776#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7777#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7778#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7779#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7780#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7781
7782/****************** Bits definition for GPIO_OSPEEDR register ***************/
7783#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7784#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
7785#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7786#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
7787#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
7788#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7789#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
7790#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7791#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
7792#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
7793#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7794#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
7795#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7796#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
7797#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
7798#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7799#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
7800#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7801#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
7802#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
7803#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7804#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
7805#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7806#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
7807#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
7808#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7809#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
7810#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7811#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
7812#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
7813#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7814#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
7815#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7816#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
7817#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
7818#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7819#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
7820#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7821#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
7822#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
7823#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7824#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
7825#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7826#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
7827#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
7828#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7829#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
7830#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7831#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
7832#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
7833#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7834#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
7835#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7836#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
7837#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
7838#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7839#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
7840#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7841#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
7842#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
7843#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7844#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
7845#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7846#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
7847#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
7848#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7849#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
7850#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7851#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
7852#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
7853#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7854#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
7855#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7856#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
7857#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
7858#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7859#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
7860#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7861#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
7862#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
7863
7864/* Legacy defines */
7865#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7866#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7867#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7868#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7869#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7870#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7871#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7872#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7873#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7874#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7875#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7876#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7877#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7878#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7879#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7880#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7881#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7882#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7883#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7884#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7885#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7886#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7887#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7888#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7889#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7890#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7891#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7892#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7893#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7894#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7895#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7896#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7897#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7898#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7899#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7900#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7901#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7902#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7903#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7904#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7905#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7906#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7907#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7908#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7909#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7910#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7911#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7912#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7913
7914/****************** Bits definition for GPIO_PUPDR register *****************/
7915#define GPIO_PUPDR_PUPD0_Pos (0U)
7916#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
7917#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7918#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
7919#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
7920#define GPIO_PUPDR_PUPD1_Pos (2U)
7921#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
7922#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7923#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
7924#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
7925#define GPIO_PUPDR_PUPD2_Pos (4U)
7926#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
7927#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7928#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
7929#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
7930#define GPIO_PUPDR_PUPD3_Pos (6U)
7931#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
7932#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7933#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
7934#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
7935#define GPIO_PUPDR_PUPD4_Pos (8U)
7936#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
7937#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7938#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
7939#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
7940#define GPIO_PUPDR_PUPD5_Pos (10U)
7941#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
7942#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7943#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
7944#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
7945#define GPIO_PUPDR_PUPD6_Pos (12U)
7946#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
7947#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7948#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
7949#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
7950#define GPIO_PUPDR_PUPD7_Pos (14U)
7951#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
7952#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7953#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
7954#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
7955#define GPIO_PUPDR_PUPD8_Pos (16U)
7956#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
7957#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7958#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
7959#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
7960#define GPIO_PUPDR_PUPD9_Pos (18U)
7961#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
7962#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7963#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
7964#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
7965#define GPIO_PUPDR_PUPD10_Pos (20U)
7966#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
7967#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
7968#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
7969#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
7970#define GPIO_PUPDR_PUPD11_Pos (22U)
7971#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
7972#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
7973#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
7974#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
7975#define GPIO_PUPDR_PUPD12_Pos (24U)
7976#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
7977#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
7978#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
7979#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
7980#define GPIO_PUPDR_PUPD13_Pos (26U)
7981#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
7982#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
7983#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
7984#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
7985#define GPIO_PUPDR_PUPD14_Pos (28U)
7986#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
7987#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
7988#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
7989#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
7990#define GPIO_PUPDR_PUPD15_Pos (30U)
7991#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
7992#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
7993#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
7994#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
7995
7996/* Legacy defines */
7997#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
7998#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
7999#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8000#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8001#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8002#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8003#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8004#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8005#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8006#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8007#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8008#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8009#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8010#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8011#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8012#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8013#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8014#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8015#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8016#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8017#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8018#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8019#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8020#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8021#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8022#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8023#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8024#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8025#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8026#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8027#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8028#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8029#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8030#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8031#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8032#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8033#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8034#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8035#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8036#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8037#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8038#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8039#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8040#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8041#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8042#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8043#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8044#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8045
8046/****************** Bits definition for GPIO_IDR register *******************/
8047#define GPIO_IDR_ID0_Pos (0U)
8048#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8049#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8050#define GPIO_IDR_ID1_Pos (1U)
8051#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8052#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8053#define GPIO_IDR_ID2_Pos (2U)
8054#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8055#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8056#define GPIO_IDR_ID3_Pos (3U)
8057#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8058#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8059#define GPIO_IDR_ID4_Pos (4U)
8060#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8061#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8062#define GPIO_IDR_ID5_Pos (5U)
8063#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8064#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8065#define GPIO_IDR_ID6_Pos (6U)
8066#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8067#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8068#define GPIO_IDR_ID7_Pos (7U)
8069#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8070#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8071#define GPIO_IDR_ID8_Pos (8U)
8072#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8073#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8074#define GPIO_IDR_ID9_Pos (9U)
8075#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8076#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8077#define GPIO_IDR_ID10_Pos (10U)
8078#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8079#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8080#define GPIO_IDR_ID11_Pos (11U)
8081#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8082#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8083#define GPIO_IDR_ID12_Pos (12U)
8084#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8085#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8086#define GPIO_IDR_ID13_Pos (13U)
8087#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8088#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8089#define GPIO_IDR_ID14_Pos (14U)
8090#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8091#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8092#define GPIO_IDR_ID15_Pos (15U)
8093#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8094#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8095
8096/* Legacy defines */
8097#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8098#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8099#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8100#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8101#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8102#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8103#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8104#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8105#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8106#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8107#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8108#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8109#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8110#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8111#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8112#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8113
8114/****************** Bits definition for GPIO_ODR register *******************/
8115#define GPIO_ODR_OD0_Pos (0U)
8116#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8117#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8118#define GPIO_ODR_OD1_Pos (1U)
8119#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8120#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8121#define GPIO_ODR_OD2_Pos (2U)
8122#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8123#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8124#define GPIO_ODR_OD3_Pos (3U)
8125#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8126#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8127#define GPIO_ODR_OD4_Pos (4U)
8128#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8129#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8130#define GPIO_ODR_OD5_Pos (5U)
8131#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8132#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8133#define GPIO_ODR_OD6_Pos (6U)
8134#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8135#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8136#define GPIO_ODR_OD7_Pos (7U)
8137#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8138#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8139#define GPIO_ODR_OD8_Pos (8U)
8140#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8141#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8142#define GPIO_ODR_OD9_Pos (9U)
8143#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8144#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8145#define GPIO_ODR_OD10_Pos (10U)
8146#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8147#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8148#define GPIO_ODR_OD11_Pos (11U)
8149#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8150#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8151#define GPIO_ODR_OD12_Pos (12U)
8152#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8153#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8154#define GPIO_ODR_OD13_Pos (13U)
8155#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8156#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8157#define GPIO_ODR_OD14_Pos (14U)
8158#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8159#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8160#define GPIO_ODR_OD15_Pos (15U)
8161#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8162#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8163/* Legacy defines */
8164#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8165#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8166#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8167#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8168#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8169#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8170#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8171#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8172#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8173#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8174#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8175#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8176#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8177#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8178#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8179#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8180
8181/****************** Bits definition for GPIO_BSRR register ******************/
8182#define GPIO_BSRR_BS0_Pos (0U)
8183#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8184#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8185#define GPIO_BSRR_BS1_Pos (1U)
8186#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8187#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8188#define GPIO_BSRR_BS2_Pos (2U)
8189#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8190#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8191#define GPIO_BSRR_BS3_Pos (3U)
8192#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8193#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8194#define GPIO_BSRR_BS4_Pos (4U)
8195#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8196#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8197#define GPIO_BSRR_BS5_Pos (5U)
8198#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8199#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8200#define GPIO_BSRR_BS6_Pos (6U)
8201#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8202#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8203#define GPIO_BSRR_BS7_Pos (7U)
8204#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8205#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8206#define GPIO_BSRR_BS8_Pos (8U)
8207#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8208#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8209#define GPIO_BSRR_BS9_Pos (9U)
8210#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8211#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8212#define GPIO_BSRR_BS10_Pos (10U)
8213#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8214#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8215#define GPIO_BSRR_BS11_Pos (11U)
8216#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8217#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8218#define GPIO_BSRR_BS12_Pos (12U)
8219#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8220#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8221#define GPIO_BSRR_BS13_Pos (13U)
8222#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8223#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8224#define GPIO_BSRR_BS14_Pos (14U)
8225#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8226#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8227#define GPIO_BSRR_BS15_Pos (15U)
8228#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8229#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8230#define GPIO_BSRR_BR0_Pos (16U)
8231#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8232#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8233#define GPIO_BSRR_BR1_Pos (17U)
8234#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8235#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8236#define GPIO_BSRR_BR2_Pos (18U)
8237#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8238#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8239#define GPIO_BSRR_BR3_Pos (19U)
8240#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8241#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8242#define GPIO_BSRR_BR4_Pos (20U)
8243#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8244#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8245#define GPIO_BSRR_BR5_Pos (21U)
8246#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8247#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8248#define GPIO_BSRR_BR6_Pos (22U)
8249#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8250#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8251#define GPIO_BSRR_BR7_Pos (23U)
8252#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8253#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8254#define GPIO_BSRR_BR8_Pos (24U)
8255#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8256#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8257#define GPIO_BSRR_BR9_Pos (25U)
8258#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8259#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8260#define GPIO_BSRR_BR10_Pos (26U)
8261#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8262#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8263#define GPIO_BSRR_BR11_Pos (27U)
8264#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8265#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8266#define GPIO_BSRR_BR12_Pos (28U)
8267#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8268#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8269#define GPIO_BSRR_BR13_Pos (29U)
8270#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8271#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8272#define GPIO_BSRR_BR14_Pos (30U)
8273#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8274#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8275#define GPIO_BSRR_BR15_Pos (31U)
8276#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8277#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8278
8279/* Legacy defines */
8280#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8281#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8282#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8283#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8284#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8285#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8286#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8287#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8288#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8289#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8290#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8291#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8292#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8293#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8294#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8295#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8296#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8297#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8298#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8299#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8300#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8301#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8302#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8303#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8304#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8305#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8306#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8307#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8308#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8309#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8310#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8311#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8312#define GPIO_BRR_BR0 GPIO_BSRR_BR0
8313#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8314#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8315#define GPIO_BRR_BR1 GPIO_BSRR_BR1
8316#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8317#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8318#define GPIO_BRR_BR2 GPIO_BSRR_BR2
8319#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8320#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8321#define GPIO_BRR_BR3 GPIO_BSRR_BR3
8322#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8323#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8324#define GPIO_BRR_BR4 GPIO_BSRR_BR4
8325#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8326#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8327#define GPIO_BRR_BR5 GPIO_BSRR_BR5
8328#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8329#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8330#define GPIO_BRR_BR6 GPIO_BSRR_BR6
8331#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8332#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8333#define GPIO_BRR_BR7 GPIO_BSRR_BR7
8334#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8335#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8336#define GPIO_BRR_BR8 GPIO_BSRR_BR8
8337#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8338#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8339#define GPIO_BRR_BR9 GPIO_BSRR_BR9
8340#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8341#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8342#define GPIO_BRR_BR10 GPIO_BSRR_BR10
8343#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8344#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8345#define GPIO_BRR_BR11 GPIO_BSRR_BR11
8346#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8347#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8348#define GPIO_BRR_BR12 GPIO_BSRR_BR12
8349#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8350#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8351#define GPIO_BRR_BR13 GPIO_BSRR_BR13
8352#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8353#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8354#define GPIO_BRR_BR14 GPIO_BSRR_BR14
8355#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8356#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8357#define GPIO_BRR_BR15 GPIO_BSRR_BR15
8358#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8359#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8360/****************** Bit definition for GPIO_LCKR register *********************/
8361#define GPIO_LCKR_LCK0_Pos (0U)
8362#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8363#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8364#define GPIO_LCKR_LCK1_Pos (1U)
8365#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8366#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8367#define GPIO_LCKR_LCK2_Pos (2U)
8368#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8369#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8370#define GPIO_LCKR_LCK3_Pos (3U)
8371#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8372#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8373#define GPIO_LCKR_LCK4_Pos (4U)
8374#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8375#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8376#define GPIO_LCKR_LCK5_Pos (5U)
8377#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8378#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8379#define GPIO_LCKR_LCK6_Pos (6U)
8380#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8381#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8382#define GPIO_LCKR_LCK7_Pos (7U)
8383#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8384#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8385#define GPIO_LCKR_LCK8_Pos (8U)
8386#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8387#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8388#define GPIO_LCKR_LCK9_Pos (9U)
8389#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8390#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8391#define GPIO_LCKR_LCK10_Pos (10U)
8392#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8393#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8394#define GPIO_LCKR_LCK11_Pos (11U)
8395#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8396#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8397#define GPIO_LCKR_LCK12_Pos (12U)
8398#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8399#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8400#define GPIO_LCKR_LCK13_Pos (13U)
8401#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8402#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8403#define GPIO_LCKR_LCK14_Pos (14U)
8404#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8405#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8406#define GPIO_LCKR_LCK15_Pos (15U)
8407#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8408#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8409#define GPIO_LCKR_LCKK_Pos (16U)
8410#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8411#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8412/****************** Bit definition for GPIO_AFRL register *********************/
8413#define GPIO_AFRL_AFSEL0_Pos (0U)
8414#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8415#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8416#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8417#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8418#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8419#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8420#define GPIO_AFRL_AFSEL1_Pos (4U)
8421#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8422#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8423#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8424#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8425#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8426#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8427#define GPIO_AFRL_AFSEL2_Pos (8U)
8428#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8429#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8430#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8431#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8432#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8433#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8434#define GPIO_AFRL_AFSEL3_Pos (12U)
8435#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8436#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8437#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8438#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8439#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8440#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8441#define GPIO_AFRL_AFSEL4_Pos (16U)
8442#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8443#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8444#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8445#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8446#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8447#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8448#define GPIO_AFRL_AFSEL5_Pos (20U)
8449#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8450#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8451#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8452#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8453#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8454#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8455#define GPIO_AFRL_AFSEL6_Pos (24U)
8456#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8457#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8458#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8459#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8460#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8461#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8462#define GPIO_AFRL_AFSEL7_Pos (28U)
8463#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8464#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8465#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8466#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8467#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8468#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8469
8470/* Legacy defines */
8471#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8472#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8473#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8474#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8475#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8476#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8477#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8478#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8479#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8480#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8481#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8482#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8483#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8484#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8485#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8486#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8487#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8488#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8489#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8490#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8491#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8492#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8493#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8494#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8495#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8496#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8497#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8498#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8499#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8500#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8501#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8502#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8503#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8504#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8505#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8506#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8507#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8508#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8509#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8510#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8511
8512/****************** Bit definition for GPIO_AFRH register *********************/
8513#define GPIO_AFRH_AFSEL8_Pos (0U)
8514#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8515#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8516#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8517#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
8518#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
8519#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
8520#define GPIO_AFRH_AFSEL9_Pos (4U)
8521#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
8522#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8523#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
8524#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
8525#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
8526#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
8527#define GPIO_AFRH_AFSEL10_Pos (8U)
8528#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
8529#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8530#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
8531#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
8532#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
8533#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
8534#define GPIO_AFRH_AFSEL11_Pos (12U)
8535#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
8536#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8537#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
8538#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
8539#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
8540#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
8541#define GPIO_AFRH_AFSEL12_Pos (16U)
8542#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
8543#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8544#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
8545#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
8546#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
8547#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
8548#define GPIO_AFRH_AFSEL13_Pos (20U)
8549#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
8550#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8551#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
8552#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
8553#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
8554#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
8555#define GPIO_AFRH_AFSEL14_Pos (24U)
8556#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
8557#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8558#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
8559#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
8560#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
8561#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8562#define GPIO_AFRH_AFSEL15_Pos (28U)
8563#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8564#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8565#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8566#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8567#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8568#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8569
8570/* Legacy defines */
8571#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8572#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8573#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8574#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8575#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8576#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8577#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8578#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8579#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8580#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8581#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8582#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8583#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8584#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8585#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8586#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8587#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8588#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8589#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8590#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8591#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8592#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8593#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8594#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8595#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8596#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8597#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8598#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8599#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8600#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8601#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8602#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8603#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8604#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8605#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8606#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8607#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8608#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8609#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8610#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8611
8612
8613/******************************************************************************/
8614/* */
8615/* Inter-integrated Circuit Interface */
8616/* */
8617/******************************************************************************/
8618/******************* Bit definition for I2C_CR1 register ********************/
8619#define I2C_CR1_PE_Pos (0U)
8620#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8621#define I2C_CR1_PE I2C_CR1_PE_Msk
8622#define I2C_CR1_SMBUS_Pos (1U)
8623#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
8624#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
8625#define I2C_CR1_SMBTYPE_Pos (3U)
8626#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
8627#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
8628#define I2C_CR1_ENARP_Pos (4U)
8629#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
8630#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
8631#define I2C_CR1_ENPEC_Pos (5U)
8632#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
8633#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
8634#define I2C_CR1_ENGC_Pos (6U)
8635#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
8636#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
8637#define I2C_CR1_NOSTRETCH_Pos (7U)
8638#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8639#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8640#define I2C_CR1_START_Pos (8U)
8641#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
8642#define I2C_CR1_START I2C_CR1_START_Msk
8643#define I2C_CR1_STOP_Pos (9U)
8644#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
8645#define I2C_CR1_STOP I2C_CR1_STOP_Msk
8646#define I2C_CR1_ACK_Pos (10U)
8647#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
8648#define I2C_CR1_ACK I2C_CR1_ACK_Msk
8649#define I2C_CR1_POS_Pos (11U)
8650#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
8651#define I2C_CR1_POS I2C_CR1_POS_Msk
8652#define I2C_CR1_PEC_Pos (12U)
8653#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
8654#define I2C_CR1_PEC I2C_CR1_PEC_Msk
8655#define I2C_CR1_ALERT_Pos (13U)
8656#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
8657#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
8658#define I2C_CR1_SWRST_Pos (15U)
8659#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8660#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8661
8662/******************* Bit definition for I2C_CR2 register ********************/
8663#define I2C_CR2_FREQ_Pos (0U)
8664#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
8665#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
8666#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
8667#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
8668#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
8669#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
8670#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
8671#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
8672
8673#define I2C_CR2_ITERREN_Pos (8U)
8674#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
8675#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
8676#define I2C_CR2_ITEVTEN_Pos (9U)
8677#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
8678#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
8679#define I2C_CR2_ITBUFEN_Pos (10U)
8680#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
8681#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
8682#define I2C_CR2_DMAEN_Pos (11U)
8683#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
8684#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
8685#define I2C_CR2_LAST_Pos (12U)
8686#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
8687#define I2C_CR2_LAST I2C_CR2_LAST_Msk
8688
8689/******************* Bit definition for I2C_OAR1 register *******************/
8690#define I2C_OAR1_ADD1_7 0x000000FEU
8691#define I2C_OAR1_ADD8_9 0x00000300U
8692
8693#define I2C_OAR1_ADD0_Pos (0U)
8694#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
8695#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
8696#define I2C_OAR1_ADD1_Pos (1U)
8697#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
8698#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
8699#define I2C_OAR1_ADD2_Pos (2U)
8700#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
8701#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
8702#define I2C_OAR1_ADD3_Pos (3U)
8703#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
8704#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
8705#define I2C_OAR1_ADD4_Pos (4U)
8706#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
8707#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
8708#define I2C_OAR1_ADD5_Pos (5U)
8709#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
8710#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
8711#define I2C_OAR1_ADD6_Pos (6U)
8712#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
8713#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
8714#define I2C_OAR1_ADD7_Pos (7U)
8715#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
8716#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
8717#define I2C_OAR1_ADD8_Pos (8U)
8718#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
8719#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
8720#define I2C_OAR1_ADD9_Pos (9U)
8721#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
8722#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
8723
8724#define I2C_OAR1_ADDMODE_Pos (15U)
8725#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
8726#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
8727
8728/******************* Bit definition for I2C_OAR2 register *******************/
8729#define I2C_OAR2_ENDUAL_Pos (0U)
8730#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
8731#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
8732#define I2C_OAR2_ADD2_Pos (1U)
8733#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
8734#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
8735
8736/******************** Bit definition for I2C_DR register ********************/
8737#define I2C_DR_DR_Pos (0U)
8738#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
8739#define I2C_DR_DR I2C_DR_DR_Msk
8740
8741/******************* Bit definition for I2C_SR1 register ********************/
8742#define I2C_SR1_SB_Pos (0U)
8743#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
8744#define I2C_SR1_SB I2C_SR1_SB_Msk
8745#define I2C_SR1_ADDR_Pos (1U)
8746#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
8747#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
8748#define I2C_SR1_BTF_Pos (2U)
8749#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
8750#define I2C_SR1_BTF I2C_SR1_BTF_Msk
8751#define I2C_SR1_ADD10_Pos (3U)
8752#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
8753#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
8754#define I2C_SR1_STOPF_Pos (4U)
8755#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
8756#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
8757#define I2C_SR1_RXNE_Pos (6U)
8758#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
8759#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
8760#define I2C_SR1_TXE_Pos (7U)
8761#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
8762#define I2C_SR1_TXE I2C_SR1_TXE_Msk
8763#define I2C_SR1_BERR_Pos (8U)
8764#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
8765#define I2C_SR1_BERR I2C_SR1_BERR_Msk
8766#define I2C_SR1_ARLO_Pos (9U)
8767#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
8768#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
8769#define I2C_SR1_AF_Pos (10U)
8770#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
8771#define I2C_SR1_AF I2C_SR1_AF_Msk
8772#define I2C_SR1_OVR_Pos (11U)
8773#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
8774#define I2C_SR1_OVR I2C_SR1_OVR_Msk
8775#define I2C_SR1_PECERR_Pos (12U)
8776#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
8777#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
8778#define I2C_SR1_TIMEOUT_Pos (14U)
8779#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
8780#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
8781#define I2C_SR1_SMBALERT_Pos (15U)
8782#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
8783#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
8784
8785/******************* Bit definition for I2C_SR2 register ********************/
8786#define I2C_SR2_MSL_Pos (0U)
8787#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
8788#define I2C_SR2_MSL I2C_SR2_MSL_Msk
8789#define I2C_SR2_BUSY_Pos (1U)
8790#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
8791#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
8792#define I2C_SR2_TRA_Pos (2U)
8793#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
8794#define I2C_SR2_TRA I2C_SR2_TRA_Msk
8795#define I2C_SR2_GENCALL_Pos (4U)
8796#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
8797#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
8798#define I2C_SR2_SMBDEFAULT_Pos (5U)
8799#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
8800#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
8801#define I2C_SR2_SMBHOST_Pos (6U)
8802#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
8803#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
8804#define I2C_SR2_DUALF_Pos (7U)
8805#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
8806#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
8807#define I2C_SR2_PEC_Pos (8U)
8808#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
8809#define I2C_SR2_PEC I2C_SR2_PEC_Msk
8810
8811/******************* Bit definition for I2C_CCR register ********************/
8812#define I2C_CCR_CCR_Pos (0U)
8813#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
8814#define I2C_CCR_CCR I2C_CCR_CCR_Msk
8815#define I2C_CCR_DUTY_Pos (14U)
8816#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
8817#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
8818#define I2C_CCR_FS_Pos (15U)
8819#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
8820#define I2C_CCR_FS I2C_CCR_FS_Msk
8821
8822/****************** Bit definition for I2C_TRISE register *******************/
8823#define I2C_TRISE_TRISE_Pos (0U)
8824#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
8825#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
8826
8827/****************** Bit definition for I2C_FLTR register *******************/
8828#define I2C_FLTR_DNF_Pos (0U)
8829#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
8830#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
8831#define I2C_FLTR_ANOFF_Pos (4U)
8832#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
8833#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
8834
8835/******************************************************************************/
8836/* */
8837/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
8838/* */
8839/******************************************************************************/
8840/******************* Bit definition for I2C_CR1 register *******************/
8841#define FMPI2C_CR1_PE_Pos (0U)
8842#define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos)
8843#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk
8844#define FMPI2C_CR1_TXIE_Pos (1U)
8845#define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos)
8846#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk
8847#define FMPI2C_CR1_RXIE_Pos (2U)
8848#define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos)
8849#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk
8850#define FMPI2C_CR1_ADDRIE_Pos (3U)
8851#define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos)
8852#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk
8853#define FMPI2C_CR1_NACKIE_Pos (4U)
8854#define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos)
8855#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk
8856#define FMPI2C_CR1_STOPIE_Pos (5U)
8857#define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos)
8858#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk
8859#define FMPI2C_CR1_TCIE_Pos (6U)
8860#define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos)
8861#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk
8862#define FMPI2C_CR1_ERRIE_Pos (7U)
8863#define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos)
8864#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk
8865#define FMPI2C_CR1_DNF_Pos (8U)
8866#define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos)
8867#define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk
8868#define FMPI2C_CR1_ANFOFF_Pos (12U)
8869#define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos)
8870#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk
8871#define FMPI2C_CR1_TXDMAEN_Pos (14U)
8872#define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)
8873#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk
8874#define FMPI2C_CR1_RXDMAEN_Pos (15U)
8875#define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)
8876#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk
8877#define FMPI2C_CR1_SBC_Pos (16U)
8878#define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos)
8879#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk
8880#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
8881#define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)
8882#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk
8883#define FMPI2C_CR1_GCEN_Pos (19U)
8884#define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos)
8885#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk
8886#define FMPI2C_CR1_SMBHEN_Pos (20U)
8887#define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos)
8888#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk
8889#define FMPI2C_CR1_SMBDEN_Pos (21U)
8890#define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos)
8891#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk
8892#define FMPI2C_CR1_ALERTEN_Pos (22U)
8893#define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos)
8894#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk
8895#define FMPI2C_CR1_PECEN_Pos (23U)
8896#define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos)
8897#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk
8898
8899/* Legacy Defines */
8900#define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
8901#define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
8902#define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
8903/****************** Bit definition for I2C_CR2 register ********************/
8904#define FMPI2C_CR2_SADD_Pos (0U)
8905#define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos)
8906#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk
8907#define FMPI2C_CR2_RD_WRN_Pos (10U)
8908#define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos)
8909#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk
8910#define FMPI2C_CR2_ADD10_Pos (11U)
8911#define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos)
8912#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk
8913#define FMPI2C_CR2_HEAD10R_Pos (12U)
8914#define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos)
8915#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk
8916#define FMPI2C_CR2_START_Pos (13U)
8917#define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos)
8918#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk
8919#define FMPI2C_CR2_STOP_Pos (14U)
8920#define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos)
8921#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk
8922#define FMPI2C_CR2_NACK_Pos (15U)
8923#define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos)
8924#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk
8925#define FMPI2C_CR2_NBYTES_Pos (16U)
8926#define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos)
8927#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk
8928#define FMPI2C_CR2_RELOAD_Pos (24U)
8929#define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos)
8930#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk
8931#define FMPI2C_CR2_AUTOEND_Pos (25U)
8932#define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos)
8933#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk
8934#define FMPI2C_CR2_PECBYTE_Pos (26U)
8935#define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos)
8936#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk
8937
8938/******************* Bit definition for I2C_OAR1 register ******************/
8939#define FMPI2C_OAR1_OA1_Pos (0U)
8940#define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos)
8941#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk
8942#define FMPI2C_OAR1_OA1MODE_Pos (10U)
8943#define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)
8944#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk
8945#define FMPI2C_OAR1_OA1EN_Pos (15U)
8946#define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos)
8947#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk
8948
8949/******************* Bit definition for I2C_OAR2 register ******************/
8950#define FMPI2C_OAR2_OA2_Pos (1U)
8951#define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos)
8952#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk
8953#define FMPI2C_OAR2_OA2MSK_Pos (8U)
8954#define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)
8955#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk
8956#define FMPI2C_OAR2_OA2EN_Pos (15U)
8957#define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos)
8958#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk
8959
8960/******************* Bit definition for I2C_TIMINGR register *******************/
8961#define FMPI2C_TIMINGR_SCLL_Pos (0U)
8962#define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)
8963#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk
8964#define FMPI2C_TIMINGR_SCLH_Pos (8U)
8965#define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)
8966#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk
8967#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
8968#define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)
8969#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk
8970#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
8971#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)
8972#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk
8973#define FMPI2C_TIMINGR_PRESC_Pos (28U)
8974#define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)
8975#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk
8976
8977/******************* Bit definition for I2C_TIMEOUTR register *******************/
8978#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8979#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos)
8980#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk
8981#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
8982#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)
8983#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk
8984#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8985#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos)
8986#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk
8987#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8988#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)
8989#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk
8990#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
8991#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)
8992#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk
8993
8994/****************** Bit definition for I2C_ISR register *********************/
8995#define FMPI2C_ISR_TXE_Pos (0U)
8996#define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos)
8997#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk
8998#define FMPI2C_ISR_TXIS_Pos (1U)
8999#define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos)
9000#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk
9001#define FMPI2C_ISR_RXNE_Pos (2U)
9002#define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos)
9003#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk
9004#define FMPI2C_ISR_ADDR_Pos (3U)
9005#define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos)
9006#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk
9007#define FMPI2C_ISR_NACKF_Pos (4U)
9008#define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos)
9009#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk
9010#define FMPI2C_ISR_STOPF_Pos (5U)
9011#define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos)
9012#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk
9013#define FMPI2C_ISR_TC_Pos (6U)
9014#define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos)
9015#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk
9016#define FMPI2C_ISR_TCR_Pos (7U)
9017#define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos)
9018#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk
9019#define FMPI2C_ISR_BERR_Pos (8U)
9020#define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos)
9021#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk
9022#define FMPI2C_ISR_ARLO_Pos (9U)
9023#define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos)
9024#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk
9025#define FMPI2C_ISR_OVR_Pos (10U)
9026#define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos)
9027#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk
9028#define FMPI2C_ISR_PECERR_Pos (11U)
9029#define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos)
9030#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk
9031#define FMPI2C_ISR_TIMEOUT_Pos (12U)
9032#define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)
9033#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk
9034#define FMPI2C_ISR_ALERT_Pos (13U)
9035#define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos)
9036#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk
9037#define FMPI2C_ISR_BUSY_Pos (15U)
9038#define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos)
9039#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk
9040#define FMPI2C_ISR_DIR_Pos (16U)
9041#define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos)
9042#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk
9043#define FMPI2C_ISR_ADDCODE_Pos (17U)
9044#define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)
9045#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk
9046
9047/****************** Bit definition for I2C_ICR register *********************/
9048#define FMPI2C_ICR_ADDRCF_Pos (3U)
9049#define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos)
9050#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk
9051#define FMPI2C_ICR_NACKCF_Pos (4U)
9052#define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos)
9053#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk
9054#define FMPI2C_ICR_STOPCF_Pos (5U)
9055#define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos)
9056#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk
9057#define FMPI2C_ICR_BERRCF_Pos (8U)
9058#define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos)
9059#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk
9060#define FMPI2C_ICR_ARLOCF_Pos (9U)
9061#define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos)
9062#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk
9063#define FMPI2C_ICR_OVRCF_Pos (10U)
9064#define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos)
9065#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk
9066#define FMPI2C_ICR_PECCF_Pos (11U)
9067#define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos)
9068#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk
9069#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
9070#define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)
9071#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk
9072#define FMPI2C_ICR_ALERTCF_Pos (13U)
9073#define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos)
9074#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk
9075
9076/****************** Bit definition for I2C_PECR register *********************/
9077#define FMPI2C_PECR_PEC_Pos (0U)
9078#define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos)
9079#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk
9080
9081/****************** Bit definition for I2C_RXDR register *********************/
9082#define FMPI2C_RXDR_RXDATA_Pos (0U)
9083#define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)
9084#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk
9085
9086/****************** Bit definition for I2C_TXDR register *********************/
9087#define FMPI2C_TXDR_TXDATA_Pos (0U)
9088#define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)
9089#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk
9090
9091
9092
9093/******************************************************************************/
9094/* */
9095/* Independent WATCHDOG */
9096/* */
9097/******************************************************************************/
9098/******************* Bit definition for IWDG_KR register ********************/
9099#define IWDG_KR_KEY_Pos (0U)
9100#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9101#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9102
9103/******************* Bit definition for IWDG_PR register ********************/
9104#define IWDG_PR_PR_Pos (0U)
9105#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9106#define IWDG_PR_PR IWDG_PR_PR_Msk
9107#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9108#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9109#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9110
9111/******************* Bit definition for IWDG_RLR register *******************/
9112#define IWDG_RLR_RL_Pos (0U)
9113#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9114#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9115
9116/******************* Bit definition for IWDG_SR register ********************/
9117#define IWDG_SR_PVU_Pos (0U)
9118#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9119#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9120#define IWDG_SR_RVU_Pos (1U)
9121#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9122#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9123
9124
9125
9126/******************************************************************************/
9127/* */
9128/* Power Control */
9129/* */
9130/******************************************************************************/
9131/******************** Bit definition for PWR_CR register ********************/
9132#define PWR_CR_LPDS_Pos (0U)
9133#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9134#define PWR_CR_LPDS PWR_CR_LPDS_Msk
9135#define PWR_CR_PDDS_Pos (1U)
9136#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9137#define PWR_CR_PDDS PWR_CR_PDDS_Msk
9138#define PWR_CR_CWUF_Pos (2U)
9139#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9140#define PWR_CR_CWUF PWR_CR_CWUF_Msk
9141#define PWR_CR_CSBF_Pos (3U)
9142#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9143#define PWR_CR_CSBF PWR_CR_CSBF_Msk
9144#define PWR_CR_PVDE_Pos (4U)
9145#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9146#define PWR_CR_PVDE PWR_CR_PVDE_Msk
9147
9148#define PWR_CR_PLS_Pos (5U)
9149#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9150#define PWR_CR_PLS PWR_CR_PLS_Msk
9151#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9152#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9153#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9154
9156#define PWR_CR_PLS_LEV0 0x00000000U
9157#define PWR_CR_PLS_LEV1 0x00000020U
9158#define PWR_CR_PLS_LEV2 0x00000040U
9159#define PWR_CR_PLS_LEV3 0x00000060U
9160#define PWR_CR_PLS_LEV4 0x00000080U
9161#define PWR_CR_PLS_LEV5 0x000000A0U
9162#define PWR_CR_PLS_LEV6 0x000000C0U
9163#define PWR_CR_PLS_LEV7 0x000000E0U
9164#define PWR_CR_DBP_Pos (8U)
9165#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9166#define PWR_CR_DBP PWR_CR_DBP_Msk
9167#define PWR_CR_FPDS_Pos (9U)
9168#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9169#define PWR_CR_FPDS PWR_CR_FPDS_Msk
9170#define PWR_CR_LPLVDS_Pos (10U)
9171#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
9172#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
9173#define PWR_CR_MRLVDS_Pos (11U)
9174#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
9175#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
9176#define PWR_CR_ADCDC1_Pos (13U)
9177#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
9178#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
9179#define PWR_CR_VOS_Pos (14U)
9180#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
9181#define PWR_CR_VOS PWR_CR_VOS_Msk
9182#define PWR_CR_VOS_0 0x00004000U
9183#define PWR_CR_VOS_1 0x00008000U
9184#define PWR_CR_FMSSR_Pos (20U)
9185#define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos)
9186#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk
9187#define PWR_CR_FISSR_Pos (21U)
9188#define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos)
9189#define PWR_CR_FISSR PWR_CR_FISSR_Msk
9190
9191
9192/******************* Bit definition for PWR_CSR register ********************/
9193#define PWR_CSR_WUF_Pos (0U)
9194#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9195#define PWR_CSR_WUF PWR_CSR_WUF_Msk
9196#define PWR_CSR_SBF_Pos (1U)
9197#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9198#define PWR_CSR_SBF PWR_CSR_SBF_Msk
9199#define PWR_CSR_PVDO_Pos (2U)
9200#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9201#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9202#define PWR_CSR_BRR_Pos (3U)
9203#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9204#define PWR_CSR_BRR PWR_CSR_BRR_Msk
9205#define PWR_CSR_EWUP3_Pos (6U)
9206#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)
9207#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk
9208#define PWR_CSR_EWUP2_Pos (7U)
9209#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
9210#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
9211#define PWR_CSR_EWUP1_Pos (8U)
9212#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
9213#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
9214#define PWR_CSR_BRE_Pos (9U)
9215#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9216#define PWR_CSR_BRE PWR_CSR_BRE_Msk
9217#define PWR_CSR_VOSRDY_Pos (14U)
9218#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9219#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9220
9221
9222/******************************************************************************/
9223/* */
9224/* QUADSPI */
9225/* */
9226/******************************************************************************/
9227/***************** Bit definition for QUADSPI_CR register *******************/
9228#define QUADSPI_CR_EN_Pos (0U)
9229#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
9230#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
9231#define QUADSPI_CR_ABORT_Pos (1U)
9232#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
9233#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
9234#define QUADSPI_CR_DMAEN_Pos (2U)
9235#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
9236#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
9237#define QUADSPI_CR_TCEN_Pos (3U)
9238#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
9239#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
9240#define QUADSPI_CR_SSHIFT_Pos (4U)
9241#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
9242#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
9243#define QUADSPI_CR_DFM_Pos (6U)
9244#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
9245#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
9246#define QUADSPI_CR_FSEL_Pos (7U)
9247#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
9248#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
9249#define QUADSPI_CR_FTHRES_Pos (8U)
9250#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
9251#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
9252#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
9253#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
9254#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
9255#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
9256#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
9257#define QUADSPI_CR_TEIE_Pos (16U)
9258#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
9259#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
9260#define QUADSPI_CR_TCIE_Pos (17U)
9261#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
9262#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
9263#define QUADSPI_CR_FTIE_Pos (18U)
9264#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
9265#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
9266#define QUADSPI_CR_SMIE_Pos (19U)
9267#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
9268#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
9269#define QUADSPI_CR_TOIE_Pos (20U)
9270#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
9271#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
9272#define QUADSPI_CR_APMS_Pos (22U)
9273#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
9274#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
9275#define QUADSPI_CR_PMM_Pos (23U)
9276#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
9277#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
9278#define QUADSPI_CR_PRESCALER_Pos (24U)
9279#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
9280#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
9281#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
9282#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
9283#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
9284#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
9285#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
9286#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
9287#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
9288#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
9289
9290/***************** Bit definition for QUADSPI_DCR register ******************/
9291#define QUADSPI_DCR_CKMODE_Pos (0U)
9292#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
9293#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
9294#define QUADSPI_DCR_CSHT_Pos (8U)
9295#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
9296#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
9297#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
9298#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
9299#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
9300#define QUADSPI_DCR_FSIZE_Pos (16U)
9301#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
9302#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
9303#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
9304#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
9305#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
9306#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
9307#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
9308
9309/****************** Bit definition for QUADSPI_SR register *******************/
9310#define QUADSPI_SR_TEF_Pos (0U)
9311#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
9312#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
9313#define QUADSPI_SR_TCF_Pos (1U)
9314#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
9315#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
9316#define QUADSPI_SR_FTF_Pos (2U)
9317#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
9318#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
9319#define QUADSPI_SR_SMF_Pos (3U)
9320#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
9321#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
9322#define QUADSPI_SR_TOF_Pos (4U)
9323#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
9324#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
9325#define QUADSPI_SR_BUSY_Pos (5U)
9326#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
9327#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
9328#define QUADSPI_SR_FLEVEL_Pos (8U)
9329#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
9330#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
9331#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
9332#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
9333#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
9334#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
9335#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
9336#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
9337
9338/****************** Bit definition for QUADSPI_FCR register ******************/
9339#define QUADSPI_FCR_CTEF_Pos (0U)
9340#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
9341#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
9342#define QUADSPI_FCR_CTCF_Pos (1U)
9343#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
9344#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
9345#define QUADSPI_FCR_CSMF_Pos (3U)
9346#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
9347#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
9348#define QUADSPI_FCR_CTOF_Pos (4U)
9349#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
9350#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
9351
9352/****************** Bit definition for QUADSPI_DLR register ******************/
9353#define QUADSPI_DLR_DL_Pos (0U)
9354#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
9355#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
9356
9357/****************** Bit definition for QUADSPI_CCR register ******************/
9358#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9359#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
9360#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
9361#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
9362#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
9363#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
9364#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
9365#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
9366#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
9367#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
9368#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
9369#define QUADSPI_CCR_IMODE_Pos (8U)
9370#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
9371#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9372#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9373#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9374#define QUADSPI_CCR_ADMODE_Pos (10U)
9375#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9376#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9377#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9378#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9379#define QUADSPI_CCR_ADSIZE_Pos (12U)
9380#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9381#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9382#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9383#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9384#define QUADSPI_CCR_ABMODE_Pos (14U)
9385#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9386#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9387#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9388#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9389#define QUADSPI_CCR_ABSIZE_Pos (16U)
9390#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9391#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9392#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9393#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9394#define QUADSPI_CCR_DCYC_Pos (18U)
9395#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9396#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9397#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9398#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9399#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9400#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9401#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9402#define QUADSPI_CCR_DMODE_Pos (24U)
9403#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9404#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9405#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9406#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9407#define QUADSPI_CCR_FMODE_Pos (26U)
9408#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9409#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9410#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9411#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9412#define QUADSPI_CCR_SIOO_Pos (28U)
9413#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9414#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9415#define QUADSPI_CCR_DHHC_Pos (30U)
9416#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9417#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9418#define QUADSPI_CCR_DDRM_Pos (31U)
9419#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9420#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9421/****************** Bit definition for QUADSPI_AR register *******************/
9422#define QUADSPI_AR_ADDRESS_Pos (0U)
9423#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9424#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9425
9426/****************** Bit definition for QUADSPI_ABR register ******************/
9427#define QUADSPI_ABR_ALTERNATE_Pos (0U)
9428#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9429#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9430
9431/****************** Bit definition for QUADSPI_DR register *******************/
9432#define QUADSPI_DR_DATA_Pos (0U)
9433#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
9434#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
9435
9436/****************** Bit definition for QUADSPI_PSMKR register ****************/
9437#define QUADSPI_PSMKR_MASK_Pos (0U)
9438#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
9439#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
9440
9441/****************** Bit definition for QUADSPI_PSMAR register ****************/
9442#define QUADSPI_PSMAR_MATCH_Pos (0U)
9443#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
9444#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
9445
9446/****************** Bit definition for QUADSPI_PIR register *****************/
9447#define QUADSPI_PIR_INTERVAL_Pos (0U)
9448#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
9449#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
9450
9451/****************** Bit definition for QUADSPI_LPTR register *****************/
9452#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9453#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
9454#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
9455
9456/******************************************************************************/
9457/* */
9458/* Reset and Clock Control */
9459/* */
9460/******************************************************************************/
9461/******************** Bit definition for RCC_CR register ********************/
9462#define RCC_CR_HSION_Pos (0U)
9463#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9464#define RCC_CR_HSION RCC_CR_HSION_Msk
9465#define RCC_CR_HSIRDY_Pos (1U)
9466#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9467#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9468
9469#define RCC_CR_HSITRIM_Pos (3U)
9470#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9471#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9472#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9473#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9474#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9475#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9476#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9477
9478#define RCC_CR_HSICAL_Pos (8U)
9479#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9480#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9481#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9482#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9483#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9484#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9485#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9486#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9487#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9488#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9489
9490#define RCC_CR_HSEON_Pos (16U)
9491#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9492#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9493#define RCC_CR_HSERDY_Pos (17U)
9494#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9495#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9496#define RCC_CR_HSEBYP_Pos (18U)
9497#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9498#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9499#define RCC_CR_CSSON_Pos (19U)
9500#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9501#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9502#define RCC_CR_PLLON_Pos (24U)
9503#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9504#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9505#define RCC_CR_PLLRDY_Pos (25U)
9506#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9507#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9508/*
9509 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9510 */
9511#define RCC_PLLI2S_SUPPORT
9512
9513#define RCC_CR_PLLI2SON_Pos (26U)
9514#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9515#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9516#define RCC_CR_PLLI2SRDY_Pos (27U)
9517#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9518#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9519
9520/******************** Bit definition for RCC_PLLCFGR register ***************/
9521#define RCC_PLLCFGR_PLLM_Pos (0U)
9522#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9523#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9524#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9525#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9526#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9527#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9528#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9529#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9530
9531#define RCC_PLLCFGR_PLLN_Pos (6U)
9532#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9533#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9534#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9535#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9536#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9537#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9538#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9539#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9540#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9541#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9542#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9543
9544#define RCC_PLLCFGR_PLLP_Pos (16U)
9545#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9546#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9547#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9548#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9549
9550#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9551#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9552#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9553#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9554#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9555#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9556#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9557
9558#define RCC_PLLCFGR_PLLQ_Pos (24U)
9559#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9560#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9561#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9562#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9563#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9564#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9565/*
9566 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9567 */
9568#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT
9569
9570#define RCC_PLLCFGR_PLLR_Pos (28U)
9571#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
9572#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9573#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
9574#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
9575#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
9576
9577/******************** Bit definition for RCC_CFGR register ******************/
9579#define RCC_CFGR_SW_Pos (0U)
9580#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9581#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9582#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9583#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9584
9585#define RCC_CFGR_SW_HSI 0x00000000U
9586#define RCC_CFGR_SW_HSE 0x00000001U
9587#define RCC_CFGR_SW_PLL 0x00000002U
9588
9590#define RCC_CFGR_SWS_Pos (2U)
9591#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9592#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9593#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9594#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9595
9596#define RCC_CFGR_SWS_HSI 0x00000000U
9597#define RCC_CFGR_SWS_HSE 0x00000004U
9598#define RCC_CFGR_SWS_PLL 0x00000008U
9599
9601#define RCC_CFGR_HPRE_Pos (4U)
9602#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9603#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9604#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9605#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9606#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9607#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9608
9609#define RCC_CFGR_HPRE_DIV1 0x00000000U
9610#define RCC_CFGR_HPRE_DIV2 0x00000080U
9611#define RCC_CFGR_HPRE_DIV4 0x00000090U
9612#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9613#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9614#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9615#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9616#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9617#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9618
9620#define RCC_CFGR_PPRE1_Pos (10U)
9621#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9622#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9623#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9624#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9625#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9626
9627#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9628#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9629#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9630#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9631#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9632
9634#define RCC_CFGR_PPRE2_Pos (13U)
9635#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9636#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9637#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9638#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9639#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9640
9641#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9642#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9643#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9644#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9645#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9646
9648#define RCC_CFGR_RTCPRE_Pos (16U)
9649#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9650#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9651#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9652#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9653#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9654#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9655#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9656
9658#define RCC_CFGR_MCO1_Pos (21U)
9659#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9660#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9661#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9662#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9663
9664
9665#define RCC_CFGR_MCO1PRE_Pos (24U)
9666#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9667#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9668#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9669#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9670#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9671
9672#define RCC_CFGR_MCO2PRE_Pos (27U)
9673#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9674#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9675#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9676#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9677#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9678
9679#define RCC_CFGR_MCO2_Pos (30U)
9680#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9681#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9682#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9683#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9684
9685/******************** Bit definition for RCC_CIR register *******************/
9686#define RCC_CIR_LSIRDYF_Pos (0U)
9687#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9688#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9689#define RCC_CIR_LSERDYF_Pos (1U)
9690#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9691#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9692#define RCC_CIR_HSIRDYF_Pos (2U)
9693#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9694#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9695#define RCC_CIR_HSERDYF_Pos (3U)
9696#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9697#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9698#define RCC_CIR_PLLRDYF_Pos (4U)
9699#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9700#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9701#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9702#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9703#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9704
9705#define RCC_CIR_CSSF_Pos (7U)
9706#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9707#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9708#define RCC_CIR_LSIRDYIE_Pos (8U)
9709#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9710#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9711#define RCC_CIR_LSERDYIE_Pos (9U)
9712#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9713#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9714#define RCC_CIR_HSIRDYIE_Pos (10U)
9715#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9716#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9717#define RCC_CIR_HSERDYIE_Pos (11U)
9718#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9719#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9720#define RCC_CIR_PLLRDYIE_Pos (12U)
9721#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9722#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9723#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9724#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9725#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9726
9727#define RCC_CIR_LSIRDYC_Pos (16U)
9728#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9729#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9730#define RCC_CIR_LSERDYC_Pos (17U)
9731#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9732#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9733#define RCC_CIR_HSIRDYC_Pos (18U)
9734#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9735#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9736#define RCC_CIR_HSERDYC_Pos (19U)
9737#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9738#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9739#define RCC_CIR_PLLRDYC_Pos (20U)
9740#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9741#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9742#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9743#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9744#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9745
9746#define RCC_CIR_CSSC_Pos (23U)
9747#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9748#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9749
9750/******************** Bit definition for RCC_AHB1RSTR register **************/
9751#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9752#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9753#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9754#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9755#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9756#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9757#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9758#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9759#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9760#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9761#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9762#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9763#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9764#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9765#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9766#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9767#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9768#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9769#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9770#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9771#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9772#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9773#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9774#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9775#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9776#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9777#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9778#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9779#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9780#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9781#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9782#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9783#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9784
9785/******************** Bit definition for RCC_AHB2RSTR register **************/
9786#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9787#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9788#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9789#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9790#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9791#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9792/******************** Bit definition for RCC_AHB3RSTR register **************/
9793#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9794#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9795#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9796#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
9797#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
9798#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9799
9800
9801/******************** Bit definition for RCC_APB1RSTR register **************/
9802#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9803#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9804#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9805#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9806#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9807#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9808#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9809#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9810#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9811#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9812#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9813#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9814#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9815#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9816#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9817#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9818#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9819#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9820#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9821#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9822#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9823#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9824#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9825#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9826#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9827#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9828#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9829#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
9830#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
9831#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
9832#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9833#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9834#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9835#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9836#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9837#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9838#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9839#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9840#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9841#define RCC_APB1RSTR_USART2RST_Pos (17U)
9842#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9843#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9844#define RCC_APB1RSTR_USART3RST_Pos (18U)
9845#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9846#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9847#define RCC_APB1RSTR_UART4RST_Pos (19U)
9848#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9849#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9850#define RCC_APB1RSTR_UART5RST_Pos (20U)
9851#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9852#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9853#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9854#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9855#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9856#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9857#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9858#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9859#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9860#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9861#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9862#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
9863#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos)
9864#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
9865#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9866#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9867#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9868#define RCC_APB1RSTR_CAN2RST_Pos (26U)
9869#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9870#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9871#define RCC_APB1RSTR_CAN3RST_Pos (27U)
9872#define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos)
9873#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
9874#define RCC_APB1RSTR_PWRRST_Pos (28U)
9875#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9876#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9877#define RCC_APB1RSTR_DACRST_Pos (29U)
9878#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9879#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9880#define RCC_APB1RSTR_UART7RST_Pos (30U)
9881#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
9882#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
9883#define RCC_APB1RSTR_UART8RST_Pos (31U)
9884#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
9885#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
9886
9887/******************** Bit definition for RCC_APB2RSTR register **************/
9888#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9889#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9890#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9891#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9892#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9893#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9894#define RCC_APB2RSTR_USART1RST_Pos (4U)
9895#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9896#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9897#define RCC_APB2RSTR_USART6RST_Pos (5U)
9898#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9899#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9900#define RCC_APB2RSTR_UART9RST_Pos (6U)
9901#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
9902#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
9903#define RCC_APB2RSTR_UART10RST_Pos (7U)
9904#define RCC_APB2RSTR_UART10RST_Msk (0x1UL << RCC_APB2RSTR_UART10RST_Pos)
9905#define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
9906#define RCC_APB2RSTR_ADCRST_Pos (8U)
9907#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9908#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9909#define RCC_APB2RSTR_SDIORST_Pos (11U)
9910#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9911#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9912#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9913#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9914#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9915#define RCC_APB2RSTR_SPI4RST_Pos (13U)
9916#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
9917#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
9918#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9919#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9920#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9921#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9922#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9923#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9924#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9925#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9926#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9927#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9928#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9929#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9930#define RCC_APB2RSTR_SPI5RST_Pos (20U)
9931#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
9932#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
9933#define RCC_APB2RSTR_SAI1RST_Pos (22U)
9934#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
9935#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9936#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
9937#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
9938#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
9939#define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
9940#define RCC_APB2RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM2RST_Pos)
9941#define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
9942
9943/******************** Bit definition for RCC_AHB1ENR register ***************/
9944#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9945#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9946#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9947#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9948#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9949#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9950#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9951#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9952#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9953#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9954#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9955#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9956#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9957#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9958#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9959#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9960#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9961#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9962#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9963#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9964#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9965#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9966#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9967#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9968#define RCC_AHB1ENR_CRCEN_Pos (12U)
9969#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9970#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9971#define RCC_AHB1ENR_DMA1EN_Pos (21U)
9972#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9973#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9974#define RCC_AHB1ENR_DMA2EN_Pos (22U)
9975#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9976#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9977/******************** Bit definition for RCC_AHB2ENR register ***************/
9978/*
9979 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9980 */
9981#define RCC_AHB2_SUPPORT
9982
9983#define RCC_AHB2ENR_RNGEN_Pos (6U)
9984#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9985#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9986#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9987#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9988#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9989
9990/******************** Bit definition for RCC_AHB3ENR register ***************/
9991/*
9992 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9993 */
9994#define RCC_AHB3_SUPPORT
9995
9996#define RCC_AHB3ENR_FSMCEN_Pos (0U)
9997#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9998#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9999#define RCC_AHB3ENR_QSPIEN_Pos (1U)
10000#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
10001#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10002
10003/******************** Bit definition for RCC_APB1ENR register ***************/
10004#define RCC_APB1ENR_TIM2EN_Pos (0U)
10005#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
10006#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
10007#define RCC_APB1ENR_TIM3EN_Pos (1U)
10008#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
10009#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
10010#define RCC_APB1ENR_TIM4EN_Pos (2U)
10011#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
10012#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
10013#define RCC_APB1ENR_TIM5EN_Pos (3U)
10014#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
10015#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
10016#define RCC_APB1ENR_TIM6EN_Pos (4U)
10017#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
10018#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
10019#define RCC_APB1ENR_TIM7EN_Pos (5U)
10020#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
10021#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10022#define RCC_APB1ENR_TIM12EN_Pos (6U)
10023#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
10024#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10025#define RCC_APB1ENR_TIM13EN_Pos (7U)
10026#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
10027#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10028#define RCC_APB1ENR_TIM14EN_Pos (8U)
10029#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
10030#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10031#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
10032#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
10033#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
10034#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
10035#define RCC_APB1ENR_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)
10036#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
10037#define RCC_APB1ENR_WWDGEN_Pos (11U)
10038#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
10039#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10040#define RCC_APB1ENR_SPI2EN_Pos (14U)
10041#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
10042#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10043#define RCC_APB1ENR_SPI3EN_Pos (15U)
10044#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
10045#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10046#define RCC_APB1ENR_USART2EN_Pos (17U)
10047#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10048#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10049#define RCC_APB1ENR_USART3EN_Pos (18U)
10050#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10051#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10052#define RCC_APB1ENR_UART4EN_Pos (19U)
10053#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10054#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10055#define RCC_APB1ENR_UART5EN_Pos (20U)
10056#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10057#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10058#define RCC_APB1ENR_I2C1EN_Pos (21U)
10059#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10060#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10061#define RCC_APB1ENR_I2C2EN_Pos (22U)
10062#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10063#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10064#define RCC_APB1ENR_I2C3EN_Pos (23U)
10065#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10066#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10067#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
10068#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos)
10069#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
10070#define RCC_APB1ENR_CAN1EN_Pos (25U)
10071#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10072#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10073#define RCC_APB1ENR_CAN2EN_Pos (26U)
10074#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10075#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10076#define RCC_APB1ENR_CAN3EN_Pos (27U)
10077#define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos)
10078#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
10079#define RCC_APB1ENR_PWREN_Pos (28U)
10080#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10081#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10082#define RCC_APB1ENR_DACEN_Pos (29U)
10083#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10084#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10085#define RCC_APB1ENR_UART7EN_Pos (30U)
10086#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
10087#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
10088#define RCC_APB1ENR_UART8EN_Pos (31U)
10089#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
10090#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
10091
10092/******************** Bit definition for RCC_APB2ENR register ***************/
10093#define RCC_APB2ENR_TIM1EN_Pos (0U)
10094#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10095#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10096#define RCC_APB2ENR_TIM8EN_Pos (1U)
10097#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10098#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10099#define RCC_APB2ENR_USART1EN_Pos (4U)
10100#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10101#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10102#define RCC_APB2ENR_USART6EN_Pos (5U)
10103#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10104#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10105#define RCC_APB2ENR_UART9EN_Pos (6U)
10106#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos)
10107#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
10108#define RCC_APB2ENR_UART10EN_Pos (7U)
10109#define RCC_APB2ENR_UART10EN_Msk (0x1UL << RCC_APB2ENR_UART10EN_Pos)
10110#define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
10111#define RCC_APB2ENR_ADC1EN_Pos (8U)
10112#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10113#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10114#define RCC_APB2ENR_SDIOEN_Pos (11U)
10115#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
10116#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10117#define RCC_APB2ENR_SPI1EN_Pos (12U)
10118#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10119#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10120#define RCC_APB2ENR_SPI4EN_Pos (13U)
10121#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
10122#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
10123#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10124#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10125#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10126#define RCC_APB2ENR_EXTITEN_Pos (15U)
10127#define RCC_APB2ENR_EXTITEN_Msk (0x1UL << RCC_APB2ENR_EXTITEN_Pos)
10128#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
10129#define RCC_APB2ENR_TIM9EN_Pos (16U)
10130#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10131#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10132#define RCC_APB2ENR_TIM10EN_Pos (17U)
10133#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10134#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10135#define RCC_APB2ENR_TIM11EN_Pos (18U)
10136#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10137#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10138#define RCC_APB2ENR_SPI5EN_Pos (20U)
10139#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
10140#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
10141#define RCC_APB2ENR_SAI1EN_Pos (22U)
10142#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
10143#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10144#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
10145#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
10146#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
10147#define RCC_APB2ENR_DFSDM2EN_Pos (25U)
10148#define RCC_APB2ENR_DFSDM2EN_Msk (0x1UL << RCC_APB2ENR_DFSDM2EN_Pos)
10149#define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
10150
10151/******************** Bit definition for RCC_AHB1LPENR register *************/
10152#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10153#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10154#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10155#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10156#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10157#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10158#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10159#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10160#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10161#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10162#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10163#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10164#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10165#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10166#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10167#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10168#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10169#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10170#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10171#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10172#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10173#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10174#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10175#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10176#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10177#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10178#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10179#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10180#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10181#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10182#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10183#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10184#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10185#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10186#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10187#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10188#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10189#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10190#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10191#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10192#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10193#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10194
10195
10196/******************** Bit definition for RCC_AHB2LPENR register *************/
10197#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10198#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
10199#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10200#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10201#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10202#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10203
10204/******************** Bit definition for RCC_AHB3LPENR register *************/
10205#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10206#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
10207#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10208#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
10209#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
10210#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
10211
10212/******************** Bit definition for RCC_APB1LPENR register *************/
10213#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10214#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10215#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10216#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10217#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10218#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10219#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10220#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10221#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10222#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10223#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10224#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10225#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10226#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10227#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10228#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10229#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10230#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10231#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10232#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10233#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10234#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10235#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10236#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10237#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10238#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10239#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10240#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
10241#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
10242#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
10243#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
10244#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos)
10245#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
10246#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10247#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10248#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10249#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10250#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10251#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10252#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10253#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10254#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10255#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10256#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10257#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10258#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10259#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10260#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10261#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10262#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10263#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10264#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10265#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10266#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10267#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10268#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10269#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10270#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10271#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10272#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10273#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10274#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10275#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10276#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
10277#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos)
10278#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
10279#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10280#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10281#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10282#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10283#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10284#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10285#define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
10286#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos)
10287#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
10288#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10289#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10290#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10291#define RCC_APB1LPENR_DACLPEN_Pos (29U)
10292#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10293#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10294#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
10295#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
10296#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
10297#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
10298#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
10299#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
10300
10301/******************** Bit definition for RCC_APB2LPENR register *************/
10302#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10303#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10304#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10305#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10306#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10307#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10308#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10309#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10310#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10311#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10312#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10313#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10314#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
10315#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
10316#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
10317#define RCC_APB2LPENR_UART10LPEN_Pos (7U)
10318#define RCC_APB2LPENR_UART10LPEN_Msk (0x1UL << RCC_APB2LPENR_UART10LPEN_Pos)
10319#define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
10320#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10321#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10322#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10323#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10324#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
10325#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10326#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10327#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10328#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10329#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10330#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
10331#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10332#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10333#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10334#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10335#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
10336#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos)
10337#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
10338#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10339#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10340#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10341#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10342#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10343#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10344#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10345#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10346#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10347#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
10348#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
10349#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
10350#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10351#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
10352#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10353#define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
10354#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
10355#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
10356#define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
10357#define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM2LPEN_Pos)
10358#define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
10359
10360/******************** Bit definition for RCC_BDCR register ******************/
10361#define RCC_BDCR_LSEON_Pos (0U)
10362#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10363#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10364#define RCC_BDCR_LSERDY_Pos (1U)
10365#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10366#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10367#define RCC_BDCR_LSEBYP_Pos (2U)
10368#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10369#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10370#define RCC_BDCR_LSEMOD_Pos (3U)
10371#define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
10372#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10373
10374#define RCC_BDCR_RTCSEL_Pos (8U)
10375#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10376#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10377#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10378#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10379
10380#define RCC_BDCR_RTCEN_Pos (15U)
10381#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10382#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10383#define RCC_BDCR_BDRST_Pos (16U)
10384#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10385#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10386
10387/******************** Bit definition for RCC_CSR register *******************/
10388#define RCC_CSR_LSION_Pos (0U)
10389#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10390#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10391#define RCC_CSR_LSIRDY_Pos (1U)
10392#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10393#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10394#define RCC_CSR_RMVF_Pos (24U)
10395#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10396#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10397#define RCC_CSR_BORRSTF_Pos (25U)
10398#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10399#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10400#define RCC_CSR_PINRSTF_Pos (26U)
10401#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10402#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10403#define RCC_CSR_PORRSTF_Pos (27U)
10404#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10405#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10406#define RCC_CSR_SFTRSTF_Pos (28U)
10407#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10408#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10409#define RCC_CSR_IWDGRSTF_Pos (29U)
10410#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10411#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10412#define RCC_CSR_WWDGRSTF_Pos (30U)
10413#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10414#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10415#define RCC_CSR_LPWRRSTF_Pos (31U)
10416#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10417#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10418/* Legacy defines */
10419#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10420#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10421
10422/******************** Bit definition for RCC_SSCGR register *****************/
10423#define RCC_SSCGR_MODPER_Pos (0U)
10424#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10425#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10426#define RCC_SSCGR_INCSTEP_Pos (13U)
10427#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10428#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10429#define RCC_SSCGR_SPREADSEL_Pos (30U)
10430#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10431#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10432#define RCC_SSCGR_SSCGEN_Pos (31U)
10433#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10434#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10435
10436/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10437#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
10438#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10439#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
10440#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10441#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10442#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10443#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10444#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10445#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10446
10447#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10448#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10449#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10450#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10451#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10452#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10453#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10454#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10455#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10456#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10457#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10458#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10459
10460#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
10461#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos)
10462#define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
10463#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10464#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10465#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10466#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10467#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10468#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10469#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10470#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10471#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10472#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10473#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10474#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10475#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10476
10477
10478
10479/******************** Bit definition for RCC_DCKCFGR register ***************/
10480#define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
10481#define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10482#define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
10483#define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10484#define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10485#define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10486#define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10487#define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10488
10489#define RCC_DCKCFGR_PLLDIVR_Pos (8U)
10490#define RCC_DCKCFGR_PLLDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos)
10491#define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
10492#define RCC_DCKCFGR_PLLDIVR_0 (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos)
10493#define RCC_DCKCFGR_PLLDIVR_1 (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos)
10494#define RCC_DCKCFGR_PLLDIVR_2 (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos)
10495#define RCC_DCKCFGR_PLLDIVR_3 (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos)
10496#define RCC_DCKCFGR_PLLDIVR_4 (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos)
10497
10498#define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
10499#define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM2ASEL_Pos)
10500#define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
10501#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
10502#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos)
10503#define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
10504
10505/*
10506 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10507 */
10508#define RCC_SAI1A_PLLSOURCE_SUPPORT
10509#define RCC_SAI1B_PLLSOURCE_SUPPORT
10510
10511#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
10512#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10513#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
10514#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10515#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10516#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
10517#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10518#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
10519#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10520#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10521#define RCC_DCKCFGR_TIMPRE_Pos (24U)
10522#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
10523#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
10524#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
10525#define RCC_DCKCFGR_I2S1SRC_Msk (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)
10526#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
10527#define RCC_DCKCFGR_I2S1SRC_0 (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)
10528#define RCC_DCKCFGR_I2S1SRC_1 (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)
10529
10530#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
10531#define RCC_DCKCFGR_I2S2SRC_Msk (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)
10532#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
10533#define RCC_DCKCFGR_I2S2SRC_0 (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)
10534#define RCC_DCKCFGR_I2S2SRC_1 (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)
10535#define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
10536#define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos)
10537#define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
10538
10539/******************** Bit definition for RCC_CKGATENR register ***************/
10540#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
10541#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos)
10542#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
10543#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
10544#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos)
10545#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
10546#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
10547#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos)
10548#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
10549#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
10550#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos)
10551#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
10552#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
10553#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos)
10554#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
10555#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
10556#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos)
10557#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
10558#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
10559#define RCC_CKGATENR_RCC_CKEN_Msk (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos)
10560#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
10561#define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
10562#define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos)
10563#define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
10564
10565/******************** Bit definition for RCC_DCKCFGR2 register ***************/
10566#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
10567#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10568#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
10569#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10570#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10571#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
10572#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
10573#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
10574#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
10575#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)
10576#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
10577#define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
10578#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10579#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
10580#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10581#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10582
10583
10584/******************************************************************************/
10585/* */
10586/* RNG */
10587/* */
10588/******************************************************************************/
10589/******************** Bits definition for RNG_CR register *******************/
10590#define RNG_CR_RNGEN_Pos (2U)
10591#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10592#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10593#define RNG_CR_IE_Pos (3U)
10594#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10595#define RNG_CR_IE RNG_CR_IE_Msk
10596
10597/******************** Bits definition for RNG_SR register *******************/
10598#define RNG_SR_DRDY_Pos (0U)
10599#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10600#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10601#define RNG_SR_CECS_Pos (1U)
10602#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10603#define RNG_SR_CECS RNG_SR_CECS_Msk
10604#define RNG_SR_SECS_Pos (2U)
10605#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10606#define RNG_SR_SECS RNG_SR_SECS_Msk
10607#define RNG_SR_CEIS_Pos (5U)
10608#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10609#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10610#define RNG_SR_SEIS_Pos (6U)
10611#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10612#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10613
10614/******************************************************************************/
10615/* */
10616/* Real-Time Clock (RTC) */
10617/* */
10618/******************************************************************************/
10619/******************** Bits definition for RTC_TR register *******************/
10620#define RTC_TR_PM_Pos (22U)
10621#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10622#define RTC_TR_PM RTC_TR_PM_Msk
10623#define RTC_TR_HT_Pos (20U)
10624#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10625#define RTC_TR_HT RTC_TR_HT_Msk
10626#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10627#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10628#define RTC_TR_HU_Pos (16U)
10629#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10630#define RTC_TR_HU RTC_TR_HU_Msk
10631#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10632#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10633#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10634#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10635#define RTC_TR_MNT_Pos (12U)
10636#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10637#define RTC_TR_MNT RTC_TR_MNT_Msk
10638#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10639#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10640#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10641#define RTC_TR_MNU_Pos (8U)
10642#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10643#define RTC_TR_MNU RTC_TR_MNU_Msk
10644#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10645#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10646#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10647#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10648#define RTC_TR_ST_Pos (4U)
10649#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10650#define RTC_TR_ST RTC_TR_ST_Msk
10651#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10652#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10653#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10654#define RTC_TR_SU_Pos (0U)
10655#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10656#define RTC_TR_SU RTC_TR_SU_Msk
10657#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10658#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10659#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10660#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10661
10662/******************** Bits definition for RTC_DR register *******************/
10663#define RTC_DR_YT_Pos (20U)
10664#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10665#define RTC_DR_YT RTC_DR_YT_Msk
10666#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10667#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10668#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10669#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10670#define RTC_DR_YU_Pos (16U)
10671#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10672#define RTC_DR_YU RTC_DR_YU_Msk
10673#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10674#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10675#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10676#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10677#define RTC_DR_WDU_Pos (13U)
10678#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10679#define RTC_DR_WDU RTC_DR_WDU_Msk
10680#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10681#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10682#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10683#define RTC_DR_MT_Pos (12U)
10684#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10685#define RTC_DR_MT RTC_DR_MT_Msk
10686#define RTC_DR_MU_Pos (8U)
10687#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10688#define RTC_DR_MU RTC_DR_MU_Msk
10689#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10690#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10691#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10692#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10693#define RTC_DR_DT_Pos (4U)
10694#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10695#define RTC_DR_DT RTC_DR_DT_Msk
10696#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10697#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10698#define RTC_DR_DU_Pos (0U)
10699#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10700#define RTC_DR_DU RTC_DR_DU_Msk
10701#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10702#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10703#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10704#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10705
10706/******************** Bits definition for RTC_CR register *******************/
10707#define RTC_CR_COE_Pos (23U)
10708#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10709#define RTC_CR_COE RTC_CR_COE_Msk
10710#define RTC_CR_OSEL_Pos (21U)
10711#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10712#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10713#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10714#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10715#define RTC_CR_POL_Pos (20U)
10716#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10717#define RTC_CR_POL RTC_CR_POL_Msk
10718#define RTC_CR_COSEL_Pos (19U)
10719#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10720#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10721#define RTC_CR_BKP_Pos (18U)
10722#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10723#define RTC_CR_BKP RTC_CR_BKP_Msk
10724#define RTC_CR_SUB1H_Pos (17U)
10725#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10726#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10727#define RTC_CR_ADD1H_Pos (16U)
10728#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10729#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10730#define RTC_CR_TSIE_Pos (15U)
10731#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10732#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10733#define RTC_CR_WUTIE_Pos (14U)
10734#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10735#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10736#define RTC_CR_ALRBIE_Pos (13U)
10737#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10738#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10739#define RTC_CR_ALRAIE_Pos (12U)
10740#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10741#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10742#define RTC_CR_TSE_Pos (11U)
10743#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10744#define RTC_CR_TSE RTC_CR_TSE_Msk
10745#define RTC_CR_WUTE_Pos (10U)
10746#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10747#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10748#define RTC_CR_ALRBE_Pos (9U)
10749#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10750#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10751#define RTC_CR_ALRAE_Pos (8U)
10752#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10753#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10754#define RTC_CR_DCE_Pos (7U)
10755#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10756#define RTC_CR_DCE RTC_CR_DCE_Msk
10757#define RTC_CR_FMT_Pos (6U)
10758#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10759#define RTC_CR_FMT RTC_CR_FMT_Msk
10760#define RTC_CR_BYPSHAD_Pos (5U)
10761#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10762#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10763#define RTC_CR_REFCKON_Pos (4U)
10764#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10765#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10766#define RTC_CR_TSEDGE_Pos (3U)
10767#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10768#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10769#define RTC_CR_WUCKSEL_Pos (0U)
10770#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10771#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10772#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10773#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10774#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10775
10776/* Legacy defines */
10777#define RTC_CR_BCK RTC_CR_BKP
10778
10779/******************** Bits definition for RTC_ISR register ******************/
10780#define RTC_ISR_RECALPF_Pos (16U)
10781#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10782#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10783#define RTC_ISR_TAMP1F_Pos (13U)
10784#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10785#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10786#define RTC_ISR_TAMP2F_Pos (14U)
10787#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10788#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10789#define RTC_ISR_TSOVF_Pos (12U)
10790#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10791#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10792#define RTC_ISR_TSF_Pos (11U)
10793#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10794#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10795#define RTC_ISR_WUTF_Pos (10U)
10796#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10797#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10798#define RTC_ISR_ALRBF_Pos (9U)
10799#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10800#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10801#define RTC_ISR_ALRAF_Pos (8U)
10802#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10803#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10804#define RTC_ISR_INIT_Pos (7U)
10805#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10806#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10807#define RTC_ISR_INITF_Pos (6U)
10808#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10809#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10810#define RTC_ISR_RSF_Pos (5U)
10811#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10812#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10813#define RTC_ISR_INITS_Pos (4U)
10814#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10815#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10816#define RTC_ISR_SHPF_Pos (3U)
10817#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10818#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10819#define RTC_ISR_WUTWF_Pos (2U)
10820#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10821#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10822#define RTC_ISR_ALRBWF_Pos (1U)
10823#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10824#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10825#define RTC_ISR_ALRAWF_Pos (0U)
10826#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10827#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10828
10829/******************** Bits definition for RTC_PRER register *****************/
10830#define RTC_PRER_PREDIV_A_Pos (16U)
10831#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10832#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10833#define RTC_PRER_PREDIV_S_Pos (0U)
10834#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10835#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10836
10837/******************** Bits definition for RTC_WUTR register *****************/
10838#define RTC_WUTR_WUT_Pos (0U)
10839#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10840#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10841
10842/******************** Bits definition for RTC_CALIBR register ***************/
10843#define RTC_CALIBR_DCS_Pos (7U)
10844#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10845#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10846#define RTC_CALIBR_DC_Pos (0U)
10847#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10848#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10849
10850/******************** Bits definition for RTC_ALRMAR register ***************/
10851#define RTC_ALRMAR_MSK4_Pos (31U)
10852#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10853#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10854#define RTC_ALRMAR_WDSEL_Pos (30U)
10855#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10856#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10857#define RTC_ALRMAR_DT_Pos (28U)
10858#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10859#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10860#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10861#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10862#define RTC_ALRMAR_DU_Pos (24U)
10863#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10864#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10865#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10866#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10867#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10868#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10869#define RTC_ALRMAR_MSK3_Pos (23U)
10870#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10871#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10872#define RTC_ALRMAR_PM_Pos (22U)
10873#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10874#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10875#define RTC_ALRMAR_HT_Pos (20U)
10876#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10877#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10878#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10879#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10880#define RTC_ALRMAR_HU_Pos (16U)
10881#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10882#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10883#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10884#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10885#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10886#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10887#define RTC_ALRMAR_MSK2_Pos (15U)
10888#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10889#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10890#define RTC_ALRMAR_MNT_Pos (12U)
10891#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10892#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10893#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10894#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10895#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10896#define RTC_ALRMAR_MNU_Pos (8U)
10897#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10898#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10899#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10900#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10901#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10902#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10903#define RTC_ALRMAR_MSK1_Pos (7U)
10904#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10905#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10906#define RTC_ALRMAR_ST_Pos (4U)
10907#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10908#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10909#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10910#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10911#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10912#define RTC_ALRMAR_SU_Pos (0U)
10913#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10914#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10915#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10916#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10917#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10918#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10919
10920/******************** Bits definition for RTC_ALRMBR register ***************/
10921#define RTC_ALRMBR_MSK4_Pos (31U)
10922#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10923#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10924#define RTC_ALRMBR_WDSEL_Pos (30U)
10925#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10926#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10927#define RTC_ALRMBR_DT_Pos (28U)
10928#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10929#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10930#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10931#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10932#define RTC_ALRMBR_DU_Pos (24U)
10933#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10934#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10935#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10936#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10937#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10938#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10939#define RTC_ALRMBR_MSK3_Pos (23U)
10940#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10941#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10942#define RTC_ALRMBR_PM_Pos (22U)
10943#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10944#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10945#define RTC_ALRMBR_HT_Pos (20U)
10946#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10947#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10948#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10949#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10950#define RTC_ALRMBR_HU_Pos (16U)
10951#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10952#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10953#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10954#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10955#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10956#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10957#define RTC_ALRMBR_MSK2_Pos (15U)
10958#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10959#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10960#define RTC_ALRMBR_MNT_Pos (12U)
10961#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10962#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10963#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10964#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10965#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10966#define RTC_ALRMBR_MNU_Pos (8U)
10967#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10968#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10969#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10970#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10971#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10972#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10973#define RTC_ALRMBR_MSK1_Pos (7U)
10974#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10975#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10976#define RTC_ALRMBR_ST_Pos (4U)
10977#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10978#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10979#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10980#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10981#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10982#define RTC_ALRMBR_SU_Pos (0U)
10983#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10984#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10985#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10986#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10987#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10988#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10989
10990/******************** Bits definition for RTC_WPR register ******************/
10991#define RTC_WPR_KEY_Pos (0U)
10992#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10993#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10994
10995/******************** Bits definition for RTC_SSR register ******************/
10996#define RTC_SSR_SS_Pos (0U)
10997#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10998#define RTC_SSR_SS RTC_SSR_SS_Msk
10999
11000/******************** Bits definition for RTC_SHIFTR register ***************/
11001#define RTC_SHIFTR_SUBFS_Pos (0U)
11002#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11003#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11004#define RTC_SHIFTR_ADD1S_Pos (31U)
11005#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11006#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11007
11008/******************** Bits definition for RTC_TSTR register *****************/
11009#define RTC_TSTR_PM_Pos (22U)
11010#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11011#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11012#define RTC_TSTR_HT_Pos (20U)
11013#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11014#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11015#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11016#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11017#define RTC_TSTR_HU_Pos (16U)
11018#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11019#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11020#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11021#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11022#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11023#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11024#define RTC_TSTR_MNT_Pos (12U)
11025#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11026#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11027#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11028#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11029#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11030#define RTC_TSTR_MNU_Pos (8U)
11031#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11032#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11033#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11034#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11035#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11036#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11037#define RTC_TSTR_ST_Pos (4U)
11038#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11039#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11040#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11041#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11042#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11043#define RTC_TSTR_SU_Pos (0U)
11044#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11045#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11046#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11047#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11048#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11049#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
11050
11051/******************** Bits definition for RTC_TSDR register *****************/
11052#define RTC_TSDR_WDU_Pos (13U)
11053#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
11054#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11055#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
11056#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
11057#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
11058#define RTC_TSDR_MT_Pos (12U)
11059#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
11060#define RTC_TSDR_MT RTC_TSDR_MT_Msk
11061#define RTC_TSDR_MU_Pos (8U)
11062#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
11063#define RTC_TSDR_MU RTC_TSDR_MU_Msk
11064#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
11065#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
11066#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
11067#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
11068#define RTC_TSDR_DT_Pos (4U)
11069#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
11070#define RTC_TSDR_DT RTC_TSDR_DT_Msk
11071#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
11072#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
11073#define RTC_TSDR_DU_Pos (0U)
11074#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
11075#define RTC_TSDR_DU RTC_TSDR_DU_Msk
11076#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
11077#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
11078#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
11079#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
11080
11081/******************** Bits definition for RTC_TSSSR register ****************/
11082#define RTC_TSSSR_SS_Pos (0U)
11083#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
11084#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11085
11086/******************** Bits definition for RTC_CAL register *****************/
11087#define RTC_CALR_CALP_Pos (15U)
11088#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
11089#define RTC_CALR_CALP RTC_CALR_CALP_Msk
11090#define RTC_CALR_CALW8_Pos (14U)
11091#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
11092#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11093#define RTC_CALR_CALW16_Pos (13U)
11094#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
11095#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11096#define RTC_CALR_CALM_Pos (0U)
11097#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
11098#define RTC_CALR_CALM RTC_CALR_CALM_Msk
11099#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
11100#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
11101#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
11102#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
11103#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
11104#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
11105#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
11106#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
11107#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
11108
11109/******************** Bits definition for RTC_TAFCR register ****************/
11110#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
11111#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
11112#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
11113#define RTC_TAFCR_TSINSEL_Pos (17U)
11114#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
11115#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
11116#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
11117#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
11118#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
11119#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
11120#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
11121#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
11122#define RTC_TAFCR_TAMPPRCH_Pos (13U)
11123#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
11124#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
11125#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
11126#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
11127#define RTC_TAFCR_TAMPFLT_Pos (11U)
11128#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
11129#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
11130#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
11131#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
11132#define RTC_TAFCR_TAMPFREQ_Pos (8U)
11133#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
11134#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
11135#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
11136#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
11137#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
11138#define RTC_TAFCR_TAMPTS_Pos (7U)
11139#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
11140#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
11141#define RTC_TAFCR_TAMP2TRG_Pos (4U)
11142#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
11143#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
11144#define RTC_TAFCR_TAMP2E_Pos (3U)
11145#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
11146#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
11147#define RTC_TAFCR_TAMPIE_Pos (2U)
11148#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
11149#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
11150#define RTC_TAFCR_TAMP1TRG_Pos (1U)
11151#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
11152#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
11153#define RTC_TAFCR_TAMP1E_Pos (0U)
11154#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
11155#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
11156
11157/* Legacy defines */
11158#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
11159
11160/******************** Bits definition for RTC_ALRMASSR register *************/
11161#define RTC_ALRMASSR_MASKSS_Pos (24U)
11162#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
11163#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11164#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
11165#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
11166#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
11167#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
11168#define RTC_ALRMASSR_SS_Pos (0U)
11169#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
11170#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11171
11172/******************** Bits definition for RTC_ALRMBSSR register *************/
11173#define RTC_ALRMBSSR_MASKSS_Pos (24U)
11174#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
11175#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11176#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
11177#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
11178#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
11179#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
11180#define RTC_ALRMBSSR_SS_Pos (0U)
11181#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
11182#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11183
11184/******************** Bits definition for RTC_BKP0R register ****************/
11185#define RTC_BKP0R_Pos (0U)
11186#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
11187#define RTC_BKP0R RTC_BKP0R_Msk
11188
11189/******************** Bits definition for RTC_BKP1R register ****************/
11190#define RTC_BKP1R_Pos (0U)
11191#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
11192#define RTC_BKP1R RTC_BKP1R_Msk
11193
11194/******************** Bits definition for RTC_BKP2R register ****************/
11195#define RTC_BKP2R_Pos (0U)
11196#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
11197#define RTC_BKP2R RTC_BKP2R_Msk
11198
11199/******************** Bits definition for RTC_BKP3R register ****************/
11200#define RTC_BKP3R_Pos (0U)
11201#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
11202#define RTC_BKP3R RTC_BKP3R_Msk
11203
11204/******************** Bits definition for RTC_BKP4R register ****************/
11205#define RTC_BKP4R_Pos (0U)
11206#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
11207#define RTC_BKP4R RTC_BKP4R_Msk
11208
11209/******************** Bits definition for RTC_BKP5R register ****************/
11210#define RTC_BKP5R_Pos (0U)
11211#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11212#define RTC_BKP5R RTC_BKP5R_Msk
11213
11214/******************** Bits definition for RTC_BKP6R register ****************/
11215#define RTC_BKP6R_Pos (0U)
11216#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11217#define RTC_BKP6R RTC_BKP6R_Msk
11218
11219/******************** Bits definition for RTC_BKP7R register ****************/
11220#define RTC_BKP7R_Pos (0U)
11221#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11222#define RTC_BKP7R RTC_BKP7R_Msk
11223
11224/******************** Bits definition for RTC_BKP8R register ****************/
11225#define RTC_BKP8R_Pos (0U)
11226#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11227#define RTC_BKP8R RTC_BKP8R_Msk
11228
11229/******************** Bits definition for RTC_BKP9R register ****************/
11230#define RTC_BKP9R_Pos (0U)
11231#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11232#define RTC_BKP9R RTC_BKP9R_Msk
11233
11234/******************** Bits definition for RTC_BKP10R register ***************/
11235#define RTC_BKP10R_Pos (0U)
11236#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11237#define RTC_BKP10R RTC_BKP10R_Msk
11238
11239/******************** Bits definition for RTC_BKP11R register ***************/
11240#define RTC_BKP11R_Pos (0U)
11241#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11242#define RTC_BKP11R RTC_BKP11R_Msk
11243
11244/******************** Bits definition for RTC_BKP12R register ***************/
11245#define RTC_BKP12R_Pos (0U)
11246#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11247#define RTC_BKP12R RTC_BKP12R_Msk
11248
11249/******************** Bits definition for RTC_BKP13R register ***************/
11250#define RTC_BKP13R_Pos (0U)
11251#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11252#define RTC_BKP13R RTC_BKP13R_Msk
11253
11254/******************** Bits definition for RTC_BKP14R register ***************/
11255#define RTC_BKP14R_Pos (0U)
11256#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11257#define RTC_BKP14R RTC_BKP14R_Msk
11258
11259/******************** Bits definition for RTC_BKP15R register ***************/
11260#define RTC_BKP15R_Pos (0U)
11261#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11262#define RTC_BKP15R RTC_BKP15R_Msk
11263
11264/******************** Bits definition for RTC_BKP16R register ***************/
11265#define RTC_BKP16R_Pos (0U)
11266#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11267#define RTC_BKP16R RTC_BKP16R_Msk
11268
11269/******************** Bits definition for RTC_BKP17R register ***************/
11270#define RTC_BKP17R_Pos (0U)
11271#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11272#define RTC_BKP17R RTC_BKP17R_Msk
11273
11274/******************** Bits definition for RTC_BKP18R register ***************/
11275#define RTC_BKP18R_Pos (0U)
11276#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11277#define RTC_BKP18R RTC_BKP18R_Msk
11278
11279/******************** Bits definition for RTC_BKP19R register ***************/
11280#define RTC_BKP19R_Pos (0U)
11281#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11282#define RTC_BKP19R RTC_BKP19R_Msk
11283
11284/******************** Number of backup registers ******************************/
11285#define RTC_BKP_NUMBER 0x000000014U
11286
11287/******************************************************************************/
11288/* */
11289/* Serial Audio Interface */
11290/* */
11291/******************************************************************************/
11292/******************** Bit definition for SAI_GCR register *******************/
11293#define SAI_GCR_SYNCIN_Pos (0U)
11294#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11295#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11296#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11297#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11298
11299#define SAI_GCR_SYNCOUT_Pos (4U)
11300#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11301#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11302#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11303#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11304
11305/******************* Bit definition for SAI_xCR1 register *******************/
11306#define SAI_xCR1_MODE_Pos (0U)
11307#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11308#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11309#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11310#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11311
11312#define SAI_xCR1_PRTCFG_Pos (2U)
11313#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11314#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11315#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11316#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11317
11318#define SAI_xCR1_DS_Pos (5U)
11319#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11320#define SAI_xCR1_DS SAI_xCR1_DS_Msk
11321#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11322#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11323#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11324
11325#define SAI_xCR1_LSBFIRST_Pos (8U)
11326#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11327#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11328#define SAI_xCR1_CKSTR_Pos (9U)
11329#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11330#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11331
11332#define SAI_xCR1_SYNCEN_Pos (10U)
11333#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11334#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11335#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11336#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11337
11338#define SAI_xCR1_MONO_Pos (12U)
11339#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11340#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11341#define SAI_xCR1_OUTDRIV_Pos (13U)
11342#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11343#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11344#define SAI_xCR1_SAIEN_Pos (16U)
11345#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11346#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11347#define SAI_xCR1_DMAEN_Pos (17U)
11348#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11349#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11350#define SAI_xCR1_NODIV_Pos (19U)
11351#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11352#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11353
11354#define SAI_xCR1_MCKDIV_Pos (20U)
11355#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11356#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11357#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11358#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11359#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11360#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11361
11362/******************* Bit definition for SAI_xCR2 register *******************/
11363#define SAI_xCR2_FTH_Pos (0U)
11364#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11365#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11366#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
11367#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
11368#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
11369
11370#define SAI_xCR2_FFLUSH_Pos (3U)
11371#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
11372#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
11373#define SAI_xCR2_TRIS_Pos (4U)
11374#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
11375#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
11376#define SAI_xCR2_MUTE_Pos (5U)
11377#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
11378#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
11379#define SAI_xCR2_MUTEVAL_Pos (6U)
11380#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
11381#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
11382
11383#define SAI_xCR2_MUTECNT_Pos (7U)
11384#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
11385#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
11386#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
11387#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
11388#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
11389#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
11390#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
11391#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
11392
11393#define SAI_xCR2_CPL_Pos (13U)
11394#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
11395#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
11396
11397#define SAI_xCR2_COMP_Pos (14U)
11398#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
11399#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
11400#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
11401#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
11402
11403/****************** Bit definition for SAI_xFRCR register *******************/
11404#define SAI_xFRCR_FRL_Pos (0U)
11405#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
11406#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
11407#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
11408#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
11409#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
11410#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
11411#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
11412#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
11413#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
11414#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
11415
11416#define SAI_xFRCR_FSALL_Pos (8U)
11417#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
11418#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
11419#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
11420#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
11421#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
11422#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
11423#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
11424#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
11425#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
11426
11427#define SAI_xFRCR_FSDEF_Pos (16U)
11428#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
11429#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
11430#define SAI_xFRCR_FSPOL_Pos (17U)
11431#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
11432#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
11433#define SAI_xFRCR_FSOFF_Pos (18U)
11434#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
11435#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
11436/* Legacy defines */
11437#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11438
11439/****************** Bit definition for SAI_xSLOTR register *******************/
11440#define SAI_xSLOTR_FBOFF_Pos (0U)
11441#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
11442#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
11443#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
11444#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
11445#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
11446#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
11447#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
11448
11449#define SAI_xSLOTR_SLOTSZ_Pos (6U)
11450#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
11451#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
11452#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
11453#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
11454
11455#define SAI_xSLOTR_NBSLOT_Pos (8U)
11456#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
11457#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
11458#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
11459#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
11460#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
11461#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
11462
11463#define SAI_xSLOTR_SLOTEN_Pos (16U)
11464#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
11465#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
11466
11467/******************* Bit definition for SAI_xIMR register *******************/
11468#define SAI_xIMR_OVRUDRIE_Pos (0U)
11469#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
11470#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
11471#define SAI_xIMR_MUTEDETIE_Pos (1U)
11472#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
11473#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
11474#define SAI_xIMR_WCKCFGIE_Pos (2U)
11475#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
11476#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
11477#define SAI_xIMR_FREQIE_Pos (3U)
11478#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
11479#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
11480#define SAI_xIMR_CNRDYIE_Pos (4U)
11481#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
11482#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
11483#define SAI_xIMR_AFSDETIE_Pos (5U)
11484#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
11485#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
11486#define SAI_xIMR_LFSDETIE_Pos (6U)
11487#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
11488#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
11489
11490/******************** Bit definition for SAI_xSR register *******************/
11491#define SAI_xSR_OVRUDR_Pos (0U)
11492#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
11493#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
11494#define SAI_xSR_MUTEDET_Pos (1U)
11495#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
11496#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
11497#define SAI_xSR_WCKCFG_Pos (2U)
11498#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
11499#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
11500#define SAI_xSR_FREQ_Pos (3U)
11501#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
11502#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
11503#define SAI_xSR_CNRDY_Pos (4U)
11504#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
11505#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
11506#define SAI_xSR_AFSDET_Pos (5U)
11507#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
11508#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
11509#define SAI_xSR_LFSDET_Pos (6U)
11510#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
11511#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
11512
11513#define SAI_xSR_FLVL_Pos (16U)
11514#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
11515#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
11516#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
11517#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
11518#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
11519
11520/****************** Bit definition for SAI_xCLRFR register ******************/
11521#define SAI_xCLRFR_COVRUDR_Pos (0U)
11522#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
11523#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
11524#define SAI_xCLRFR_CMUTEDET_Pos (1U)
11525#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
11526#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
11527#define SAI_xCLRFR_CWCKCFG_Pos (2U)
11528#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
11529#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
11530#define SAI_xCLRFR_CFREQ_Pos (3U)
11531#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
11532#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
11533#define SAI_xCLRFR_CCNRDY_Pos (4U)
11534#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
11535#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
11536#define SAI_xCLRFR_CAFSDET_Pos (5U)
11537#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
11538#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
11539#define SAI_xCLRFR_CLFSDET_Pos (6U)
11540#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
11541#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
11542
11543/****************** Bit definition for SAI_xDR register ******************/
11544#define SAI_xDR_DATA_Pos (0U)
11545#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
11546#define SAI_xDR_DATA SAI_xDR_DATA_Msk
11547
11548
11549/******************************************************************************/
11550/* */
11551/* SD host Interface */
11552/* */
11553/******************************************************************************/
11554/****************** Bit definition for SDIO_POWER register ******************/
11555#define SDIO_POWER_PWRCTRL_Pos (0U)
11556#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
11557#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
11558#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
11559#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
11560
11561/****************** Bit definition for SDIO_CLKCR register ******************/
11562#define SDIO_CLKCR_CLKDIV_Pos (0U)
11563#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
11564#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
11565#define SDIO_CLKCR_CLKEN_Pos (8U)
11566#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
11567#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
11568#define SDIO_CLKCR_PWRSAV_Pos (9U)
11569#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
11570#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
11571#define SDIO_CLKCR_BYPASS_Pos (10U)
11572#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
11573#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
11574
11575#define SDIO_CLKCR_WIDBUS_Pos (11U)
11576#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
11577#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
11578#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
11579#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
11580
11581#define SDIO_CLKCR_NEGEDGE_Pos (13U)
11582#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
11583#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
11584#define SDIO_CLKCR_HWFC_EN_Pos (14U)
11585#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
11586#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
11587
11588/******************* Bit definition for SDIO_ARG register *******************/
11589#define SDIO_ARG_CMDARG_Pos (0U)
11590#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
11591#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
11592
11593/******************* Bit definition for SDIO_CMD register *******************/
11594#define SDIO_CMD_CMDINDEX_Pos (0U)
11595#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
11596#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
11597
11598#define SDIO_CMD_WAITRESP_Pos (6U)
11599#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
11600#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
11601#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
11602#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
11603
11604#define SDIO_CMD_WAITINT_Pos (8U)
11605#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
11606#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
11607#define SDIO_CMD_WAITPEND_Pos (9U)
11608#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
11609#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
11610#define SDIO_CMD_CPSMEN_Pos (10U)
11611#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
11612#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
11613#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11614#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
11615#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
11616
11617/***************** Bit definition for SDIO_RESPCMD register *****************/
11618#define SDIO_RESPCMD_RESPCMD_Pos (0U)
11619#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
11620#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
11621
11622/****************** Bit definition for SDIO_RESP0 register ******************/
11623#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11624#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
11625#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
11626
11627/****************** Bit definition for SDIO_RESP1 register ******************/
11628#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11629#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
11630#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
11631
11632/****************** Bit definition for SDIO_RESP2 register ******************/
11633#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11634#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
11635#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
11636
11637/****************** Bit definition for SDIO_RESP3 register ******************/
11638#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11639#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
11640#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
11641
11642/****************** Bit definition for SDIO_RESP4 register ******************/
11643#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11644#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
11645#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
11646
11647/****************** Bit definition for SDIO_DTIMER register *****************/
11648#define SDIO_DTIMER_DATATIME_Pos (0U)
11649#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
11650#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
11651
11652/****************** Bit definition for SDIO_DLEN register *******************/
11653#define SDIO_DLEN_DATALENGTH_Pos (0U)
11654#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
11655#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
11656
11657/****************** Bit definition for SDIO_DCTRL register ******************/
11658#define SDIO_DCTRL_DTEN_Pos (0U)
11659#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
11660#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
11661#define SDIO_DCTRL_DTDIR_Pos (1U)
11662#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
11663#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
11664#define SDIO_DCTRL_DTMODE_Pos (2U)
11665#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
11666#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
11667#define SDIO_DCTRL_DMAEN_Pos (3U)
11668#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
11669#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
11670
11671#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11672#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11673#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
11674#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11675#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11676#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11677#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11678
11679#define SDIO_DCTRL_RWSTART_Pos (8U)
11680#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
11681#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
11682#define SDIO_DCTRL_RWSTOP_Pos (9U)
11683#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
11684#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
11685#define SDIO_DCTRL_RWMOD_Pos (10U)
11686#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
11687#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
11688#define SDIO_DCTRL_SDIOEN_Pos (11U)
11689#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
11690#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
11691
11692/****************** Bit definition for SDIO_DCOUNT register *****************/
11693#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11694#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
11695#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
11696
11697/****************** Bit definition for SDIO_STA register ********************/
11698#define SDIO_STA_CCRCFAIL_Pos (0U)
11699#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
11700#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
11701#define SDIO_STA_DCRCFAIL_Pos (1U)
11702#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
11703#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
11704#define SDIO_STA_CTIMEOUT_Pos (2U)
11705#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
11706#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
11707#define SDIO_STA_DTIMEOUT_Pos (3U)
11708#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
11709#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
11710#define SDIO_STA_TXUNDERR_Pos (4U)
11711#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
11712#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
11713#define SDIO_STA_RXOVERR_Pos (5U)
11714#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
11715#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
11716#define SDIO_STA_CMDREND_Pos (6U)
11717#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
11718#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
11719#define SDIO_STA_CMDSENT_Pos (7U)
11720#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
11721#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
11722#define SDIO_STA_DATAEND_Pos (8U)
11723#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
11724#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
11725#define SDIO_STA_DBCKEND_Pos (10U)
11726#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
11727#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
11728#define SDIO_STA_CMDACT_Pos (11U)
11729#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
11730#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
11731#define SDIO_STA_TXACT_Pos (12U)
11732#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
11733#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
11734#define SDIO_STA_RXACT_Pos (13U)
11735#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
11736#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
11737#define SDIO_STA_TXFIFOHE_Pos (14U)
11738#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
11739#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
11740#define SDIO_STA_RXFIFOHF_Pos (15U)
11741#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
11742#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
11743#define SDIO_STA_TXFIFOF_Pos (16U)
11744#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
11745#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
11746#define SDIO_STA_RXFIFOF_Pos (17U)
11747#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
11748#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
11749#define SDIO_STA_TXFIFOE_Pos (18U)
11750#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
11751#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
11752#define SDIO_STA_RXFIFOE_Pos (19U)
11753#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
11754#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
11755#define SDIO_STA_TXDAVL_Pos (20U)
11756#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
11757#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
11758#define SDIO_STA_RXDAVL_Pos (21U)
11759#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
11760#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
11761#define SDIO_STA_SDIOIT_Pos (22U)
11762#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
11763#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
11764
11765/******************* Bit definition for SDIO_ICR register *******************/
11766#define SDIO_ICR_CCRCFAILC_Pos (0U)
11767#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
11768#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
11769#define SDIO_ICR_DCRCFAILC_Pos (1U)
11770#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
11771#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
11772#define SDIO_ICR_CTIMEOUTC_Pos (2U)
11773#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
11774#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
11775#define SDIO_ICR_DTIMEOUTC_Pos (3U)
11776#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
11777#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
11778#define SDIO_ICR_TXUNDERRC_Pos (4U)
11779#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
11780#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
11781#define SDIO_ICR_RXOVERRC_Pos (5U)
11782#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11783#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11784#define SDIO_ICR_CMDRENDC_Pos (6U)
11785#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11786#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11787#define SDIO_ICR_CMDSENTC_Pos (7U)
11788#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11789#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11790#define SDIO_ICR_DATAENDC_Pos (8U)
11791#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11792#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11793#define SDIO_ICR_DBCKENDC_Pos (10U)
11794#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11795#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11796#define SDIO_ICR_SDIOITC_Pos (22U)
11797#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11798#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11799
11800/****************** Bit definition for SDIO_MASK register *******************/
11801#define SDIO_MASK_CCRCFAILIE_Pos (0U)
11802#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11803#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11804#define SDIO_MASK_DCRCFAILIE_Pos (1U)
11805#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11806#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11807#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11808#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11809#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11810#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11811#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11812#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11813#define SDIO_MASK_TXUNDERRIE_Pos (4U)
11814#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11815#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11816#define SDIO_MASK_RXOVERRIE_Pos (5U)
11817#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11818#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11819#define SDIO_MASK_CMDRENDIE_Pos (6U)
11820#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11821#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11822#define SDIO_MASK_CMDSENTIE_Pos (7U)
11823#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11824#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11825#define SDIO_MASK_DATAENDIE_Pos (8U)
11826#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11827#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11828#define SDIO_MASK_DBCKENDIE_Pos (10U)
11829#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11830#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11831#define SDIO_MASK_CMDACTIE_Pos (11U)
11832#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11833#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11834#define SDIO_MASK_TXACTIE_Pos (12U)
11835#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11836#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11837#define SDIO_MASK_RXACTIE_Pos (13U)
11838#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11839#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11840#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11841#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11842#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11843#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11844#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11845#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11846#define SDIO_MASK_TXFIFOFIE_Pos (16U)
11847#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11848#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11849#define SDIO_MASK_RXFIFOFIE_Pos (17U)
11850#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
11851#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
11852#define SDIO_MASK_TXFIFOEIE_Pos (18U)
11853#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
11854#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
11855#define SDIO_MASK_RXFIFOEIE_Pos (19U)
11856#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
11857#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
11858#define SDIO_MASK_TXDAVLIE_Pos (20U)
11859#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
11860#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
11861#define SDIO_MASK_RXDAVLIE_Pos (21U)
11862#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
11863#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
11864#define SDIO_MASK_SDIOITIE_Pos (22U)
11865#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
11866#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
11867
11868/***************** Bit definition for SDIO_FIFOCNT register *****************/
11869#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11870#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
11871#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
11872
11873/****************** Bit definition for SDIO_FIFO register *******************/
11874#define SDIO_FIFO_FIFODATA_Pos (0U)
11875#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
11876#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
11877
11878/******************************************************************************/
11879/* */
11880/* Serial Peripheral Interface */
11881/* */
11882/******************************************************************************/
11883#define SPI_I2S_FULLDUPLEX_SUPPORT
11884#define I2S_APB1_APB2_FEATURE
11885
11886/******************* Bit definition for SPI_CR1 register ********************/
11887#define SPI_CR1_CPHA_Pos (0U)
11888#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11889#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11890#define SPI_CR1_CPOL_Pos (1U)
11891#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11892#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11893#define SPI_CR1_MSTR_Pos (2U)
11894#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11895#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11896
11897#define SPI_CR1_BR_Pos (3U)
11898#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11899#define SPI_CR1_BR SPI_CR1_BR_Msk
11900#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11901#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11902#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11903
11904#define SPI_CR1_SPE_Pos (6U)
11905#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11906#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11907#define SPI_CR1_LSBFIRST_Pos (7U)
11908#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11909#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11910#define SPI_CR1_SSI_Pos (8U)
11911#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11912#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11913#define SPI_CR1_SSM_Pos (9U)
11914#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11915#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11916#define SPI_CR1_RXONLY_Pos (10U)
11917#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11918#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11919#define SPI_CR1_DFF_Pos (11U)
11920#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11921#define SPI_CR1_DFF SPI_CR1_DFF_Msk
11922#define SPI_CR1_CRCNEXT_Pos (12U)
11923#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11924#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11925#define SPI_CR1_CRCEN_Pos (13U)
11926#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11927#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11928#define SPI_CR1_BIDIOE_Pos (14U)
11929#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11930#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11931#define SPI_CR1_BIDIMODE_Pos (15U)
11932#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11933#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11934
11935/******************* Bit definition for SPI_CR2 register ********************/
11936#define SPI_CR2_RXDMAEN_Pos (0U)
11937#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11938#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11939#define SPI_CR2_TXDMAEN_Pos (1U)
11940#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11941#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11942#define SPI_CR2_SSOE_Pos (2U)
11943#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11944#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11945#define SPI_CR2_FRF_Pos (4U)
11946#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11947#define SPI_CR2_FRF SPI_CR2_FRF_Msk
11948#define SPI_CR2_ERRIE_Pos (5U)
11949#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11950#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11951#define SPI_CR2_RXNEIE_Pos (6U)
11952#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11953#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11954#define SPI_CR2_TXEIE_Pos (7U)
11955#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11956#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11957
11958/******************** Bit definition for SPI_SR register ********************/
11959#define SPI_SR_RXNE_Pos (0U)
11960#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11961#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11962#define SPI_SR_TXE_Pos (1U)
11963#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11964#define SPI_SR_TXE SPI_SR_TXE_Msk
11965#define SPI_SR_CHSIDE_Pos (2U)
11966#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11967#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11968#define SPI_SR_UDR_Pos (3U)
11969#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11970#define SPI_SR_UDR SPI_SR_UDR_Msk
11971#define SPI_SR_CRCERR_Pos (4U)
11972#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11973#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11974#define SPI_SR_MODF_Pos (5U)
11975#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11976#define SPI_SR_MODF SPI_SR_MODF_Msk
11977#define SPI_SR_OVR_Pos (6U)
11978#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11979#define SPI_SR_OVR SPI_SR_OVR_Msk
11980#define SPI_SR_BSY_Pos (7U)
11981#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11982#define SPI_SR_BSY SPI_SR_BSY_Msk
11983#define SPI_SR_FRE_Pos (8U)
11984#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11985#define SPI_SR_FRE SPI_SR_FRE_Msk
11986
11987/******************** Bit definition for SPI_DR register ********************/
11988#define SPI_DR_DR_Pos (0U)
11989#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11990#define SPI_DR_DR SPI_DR_DR_Msk
11991
11992/******************* Bit definition for SPI_CRCPR register ******************/
11993#define SPI_CRCPR_CRCPOLY_Pos (0U)
11994#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11995#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11996
11997/****************** Bit definition for SPI_RXCRCR register ******************/
11998#define SPI_RXCRCR_RXCRC_Pos (0U)
11999#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
12000#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
12001
12002/****************** Bit definition for SPI_TXCRCR register ******************/
12003#define SPI_TXCRCR_TXCRC_Pos (0U)
12004#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
12005#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
12006
12007/****************** Bit definition for SPI_I2SCFGR register *****************/
12008#define SPI_I2SCFGR_CHLEN_Pos (0U)
12009#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
12010#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
12011
12012#define SPI_I2SCFGR_DATLEN_Pos (1U)
12013#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
12014#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
12015#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
12016#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
12017
12018#define SPI_I2SCFGR_CKPOL_Pos (3U)
12019#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
12020#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
12021
12022#define SPI_I2SCFGR_I2SSTD_Pos (4U)
12023#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
12024#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
12025#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
12026#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
12027
12028#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12029#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
12030#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12031
12032#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12033#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12034#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12035#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12036#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12037
12038#define SPI_I2SCFGR_I2SE_Pos (10U)
12039#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12040#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12041#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12042#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12043#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12044#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
12045#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
12046#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
12047
12048/****************** Bit definition for SPI_I2SPR register *******************/
12049#define SPI_I2SPR_I2SDIV_Pos (0U)
12050#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12051#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12052#define SPI_I2SPR_ODD_Pos (8U)
12053#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12054#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12055#define SPI_I2SPR_MCKOE_Pos (9U)
12056#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12057#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12058
12059/******************************************************************************/
12060/* */
12061/* SYSCFG */
12062/* */
12063/******************************************************************************/
12064/****************** Bit definition for SYSCFG_MEMRMP register ***************/
12065#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
12066#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12067#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
12068#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12069#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12070/****************** Bit definition for SYSCFG_PMC register ******************/
12071#define SYSCFG_PMC_ADC1DC2_Pos (16U)
12072#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
12073#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
12074
12075/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12076#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12077#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
12078#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12079#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12080#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
12081#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12082#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12083#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
12084#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12085#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12086#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
12087#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12091#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
12092#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
12093#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
12094#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
12095#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
12096#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
12097#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
12098#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
12099
12103#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
12104#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
12105#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
12106#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
12107#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
12108#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
12109#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
12110#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
12111
12115#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
12116#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
12117#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
12118#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
12119#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
12120#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
12121#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
12122#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
12123
12127#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
12128#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
12129#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
12130#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
12131#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
12132#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
12133#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
12134#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
12135
12136/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12137#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12138#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
12139#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
12140#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12141#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
12142#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
12143#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12144#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
12145#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
12146#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12147#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
12148#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
12149
12153#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
12154#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
12155#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
12156#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
12157#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
12158#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
12159#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
12160#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
12161
12165#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
12166#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
12167#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
12168#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
12169#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
12170#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
12171#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
12172#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
12173
12177#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
12178#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
12179#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
12180#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
12181#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
12182#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
12183#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
12184#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
12185
12189#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
12190#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
12191#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
12192#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
12193#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
12194#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
12195#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
12196#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
12197
12198/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12199#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12200#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
12201#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
12202#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12203#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
12204#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
12205#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12206#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
12207#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
12208#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12209#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
12210#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12211
12215#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
12216#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
12217#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
12218#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
12219#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
12220#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
12221#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
12222#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
12223
12227#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
12228#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
12229#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
12230#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
12231#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
12232#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
12233#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
12234#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
12235
12239#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
12240#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
12241#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
12242#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
12243#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
12244#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
12245#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
12246#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
12247
12251#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
12252#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
12253#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
12254#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
12255#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
12256#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
12257#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
12258#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
12259
12260/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12261#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12262#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
12263#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
12264#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12265#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
12266#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
12267#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12268#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
12269#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
12270#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12271#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
12272#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
12273
12277#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
12278#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
12279#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
12280#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
12281#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
12282#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
12283#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
12284#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
12285
12289#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
12290#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
12291#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
12292#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
12293#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
12294#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
12295#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
12296#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
12297
12301#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
12302#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
12303#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
12304#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
12305#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
12306#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
12307#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
12308#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
12309
12313#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
12314#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
12315#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
12316#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
12317#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
12318#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
12319#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
12320#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
12321
12322/****************** Bit definition for SYSCFG_CMPCR register ****************/
12323#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
12324#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
12325#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
12326#define SYSCFG_CMPCR_READY_Pos (8U)
12327#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
12328#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
12329/****************** Bit definition for SYSCFG_CFGR register *****************/
12330#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
12331#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos)
12332#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk
12333#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
12334#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos)
12335#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk
12336
12337/****************** Bit definition for SYSCFG_CFGR2 register *****************/
12338#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
12339#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)
12340#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk
12341#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
12342#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)
12343#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk
12344/****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
12345#define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
12346#define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_BSCKSEL_Pos)
12347#define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk
12348#define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
12349#define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos)
12350#define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk
12351#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
12352#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos)
12353#define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk
12354#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
12355#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos)
12356#define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk
12357#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
12358#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos)
12359#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk
12360#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
12361#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos)
12362#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk
12363#define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
12364#define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos)
12365#define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk
12366#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
12367#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos)
12368#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk
12369#define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
12370#define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos)
12371#define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk
12372#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
12373#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos)
12374#define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk
12375#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
12376#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos)
12377#define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk
12378#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
12379#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos)
12380#define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk
12381#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
12382#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos)
12383#define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk
12384#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
12385#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos)
12386#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk
12387#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
12388#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos)
12389#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk
12390#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
12391#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos)
12392#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk
12393#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
12394#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos)
12395#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk
12396#define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
12397#define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos)
12398#define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk
12399#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
12400#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos)
12401#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk
12402
12403/******************************************************************************/
12404/* */
12405/* TIM */
12406/* */
12407/******************************************************************************/
12408/******************* Bit definition for TIM_CR1 register ********************/
12409#define TIM_CR1_CEN_Pos (0U)
12410#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
12411#define TIM_CR1_CEN TIM_CR1_CEN_Msk
12412#define TIM_CR1_UDIS_Pos (1U)
12413#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
12414#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
12415#define TIM_CR1_URS_Pos (2U)
12416#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
12417#define TIM_CR1_URS TIM_CR1_URS_Msk
12418#define TIM_CR1_OPM_Pos (3U)
12419#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
12420#define TIM_CR1_OPM TIM_CR1_OPM_Msk
12421#define TIM_CR1_DIR_Pos (4U)
12422#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
12423#define TIM_CR1_DIR TIM_CR1_DIR_Msk
12424
12425#define TIM_CR1_CMS_Pos (5U)
12426#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
12427#define TIM_CR1_CMS TIM_CR1_CMS_Msk
12428#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
12429#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
12430
12431#define TIM_CR1_ARPE_Pos (7U)
12432#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
12433#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
12434
12435#define TIM_CR1_CKD_Pos (8U)
12436#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
12437#define TIM_CR1_CKD TIM_CR1_CKD_Msk
12438#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
12439#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
12440
12441/******************* Bit definition for TIM_CR2 register ********************/
12442#define TIM_CR2_CCPC_Pos (0U)
12443#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
12444#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
12445#define TIM_CR2_CCUS_Pos (2U)
12446#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
12447#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
12448#define TIM_CR2_CCDS_Pos (3U)
12449#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
12450#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
12451
12452#define TIM_CR2_MMS_Pos (4U)
12453#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
12454#define TIM_CR2_MMS TIM_CR2_MMS_Msk
12455#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
12456#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
12457#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
12458
12459#define TIM_CR2_TI1S_Pos (7U)
12460#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
12461#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
12462#define TIM_CR2_OIS1_Pos (8U)
12463#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
12464#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
12465#define TIM_CR2_OIS1N_Pos (9U)
12466#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
12467#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
12468#define TIM_CR2_OIS2_Pos (10U)
12469#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
12470#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
12471#define TIM_CR2_OIS2N_Pos (11U)
12472#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
12473#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
12474#define TIM_CR2_OIS3_Pos (12U)
12475#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
12476#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
12477#define TIM_CR2_OIS3N_Pos (13U)
12478#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
12479#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
12480#define TIM_CR2_OIS4_Pos (14U)
12481#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
12482#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
12483
12484/******************* Bit definition for TIM_SMCR register *******************/
12485#define TIM_SMCR_SMS_Pos (0U)
12486#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
12487#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
12488#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
12489#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
12490#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
12491
12492#define TIM_SMCR_TS_Pos (4U)
12493#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
12494#define TIM_SMCR_TS TIM_SMCR_TS_Msk
12495#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
12496#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
12497#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12498
12499#define TIM_SMCR_MSM_Pos (7U)
12500#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12501#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12502
12503#define TIM_SMCR_ETF_Pos (8U)
12504#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12505#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12506#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12507#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12508#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12509#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12510
12511#define TIM_SMCR_ETPS_Pos (12U)
12512#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12513#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12514#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12515#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12516
12517#define TIM_SMCR_ECE_Pos (14U)
12518#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12519#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12520#define TIM_SMCR_ETP_Pos (15U)
12521#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12522#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12523
12524/******************* Bit definition for TIM_DIER register *******************/
12525#define TIM_DIER_UIE_Pos (0U)
12526#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12527#define TIM_DIER_UIE TIM_DIER_UIE_Msk
12528#define TIM_DIER_CC1IE_Pos (1U)
12529#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12530#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12531#define TIM_DIER_CC2IE_Pos (2U)
12532#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12533#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12534#define TIM_DIER_CC3IE_Pos (3U)
12535#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12536#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12537#define TIM_DIER_CC4IE_Pos (4U)
12538#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12539#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12540#define TIM_DIER_COMIE_Pos (5U)
12541#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12542#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12543#define TIM_DIER_TIE_Pos (6U)
12544#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12545#define TIM_DIER_TIE TIM_DIER_TIE_Msk
12546#define TIM_DIER_BIE_Pos (7U)
12547#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12548#define TIM_DIER_BIE TIM_DIER_BIE_Msk
12549#define TIM_DIER_UDE_Pos (8U)
12550#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12551#define TIM_DIER_UDE TIM_DIER_UDE_Msk
12552#define TIM_DIER_CC1DE_Pos (9U)
12553#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12554#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12555#define TIM_DIER_CC2DE_Pos (10U)
12556#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12557#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12558#define TIM_DIER_CC3DE_Pos (11U)
12559#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12560#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12561#define TIM_DIER_CC4DE_Pos (12U)
12562#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12563#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12564#define TIM_DIER_COMDE_Pos (13U)
12565#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12566#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12567#define TIM_DIER_TDE_Pos (14U)
12568#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12569#define TIM_DIER_TDE TIM_DIER_TDE_Msk
12570
12571/******************** Bit definition for TIM_SR register ********************/
12572#define TIM_SR_UIF_Pos (0U)
12573#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12574#define TIM_SR_UIF TIM_SR_UIF_Msk
12575#define TIM_SR_CC1IF_Pos (1U)
12576#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12577#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12578#define TIM_SR_CC2IF_Pos (2U)
12579#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12580#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12581#define TIM_SR_CC3IF_Pos (3U)
12582#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12583#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12584#define TIM_SR_CC4IF_Pos (4U)
12585#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12586#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12587#define TIM_SR_COMIF_Pos (5U)
12588#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12589#define TIM_SR_COMIF TIM_SR_COMIF_Msk
12590#define TIM_SR_TIF_Pos (6U)
12591#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12592#define TIM_SR_TIF TIM_SR_TIF_Msk
12593#define TIM_SR_BIF_Pos (7U)
12594#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12595#define TIM_SR_BIF TIM_SR_BIF_Msk
12596#define TIM_SR_CC1OF_Pos (9U)
12597#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12598#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12599#define TIM_SR_CC2OF_Pos (10U)
12600#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12601#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12602#define TIM_SR_CC3OF_Pos (11U)
12603#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12604#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12605#define TIM_SR_CC4OF_Pos (12U)
12606#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12607#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12608
12609/******************* Bit definition for TIM_EGR register ********************/
12610#define TIM_EGR_UG_Pos (0U)
12611#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12612#define TIM_EGR_UG TIM_EGR_UG_Msk
12613#define TIM_EGR_CC1G_Pos (1U)
12614#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12615#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12616#define TIM_EGR_CC2G_Pos (2U)
12617#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12618#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12619#define TIM_EGR_CC3G_Pos (3U)
12620#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12621#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12622#define TIM_EGR_CC4G_Pos (4U)
12623#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12624#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12625#define TIM_EGR_COMG_Pos (5U)
12626#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12627#define TIM_EGR_COMG TIM_EGR_COMG_Msk
12628#define TIM_EGR_TG_Pos (6U)
12629#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12630#define TIM_EGR_TG TIM_EGR_TG_Msk
12631#define TIM_EGR_BG_Pos (7U)
12632#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12633#define TIM_EGR_BG TIM_EGR_BG_Msk
12634
12635/****************** Bit definition for TIM_CCMR1 register *******************/
12636#define TIM_CCMR1_CC1S_Pos (0U)
12637#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12638#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12639#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12640#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12641
12642#define TIM_CCMR1_OC1FE_Pos (2U)
12643#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12644#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12645#define TIM_CCMR1_OC1PE_Pos (3U)
12646#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12647#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12648
12649#define TIM_CCMR1_OC1M_Pos (4U)
12650#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
12651#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12652#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
12653#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
12654#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
12655
12656#define TIM_CCMR1_OC1CE_Pos (7U)
12657#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12658#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12659
12660#define TIM_CCMR1_CC2S_Pos (8U)
12661#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12662#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12663#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12664#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12665
12666#define TIM_CCMR1_OC2FE_Pos (10U)
12667#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12668#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12669#define TIM_CCMR1_OC2PE_Pos (11U)
12670#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12671#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12672
12673#define TIM_CCMR1_OC2M_Pos (12U)
12674#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
12675#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12676#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
12677#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
12678#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
12679
12680#define TIM_CCMR1_OC2CE_Pos (15U)
12681#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12682#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12683
12684/*----------------------------------------------------------------------------*/
12685
12686#define TIM_CCMR1_IC1PSC_Pos (2U)
12687#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12688#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12689#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12690#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12691
12692#define TIM_CCMR1_IC1F_Pos (4U)
12693#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12694#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12695#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12696#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12697#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12698#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12699
12700#define TIM_CCMR1_IC2PSC_Pos (10U)
12701#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12702#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12703#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12704#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12705
12706#define TIM_CCMR1_IC2F_Pos (12U)
12707#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12708#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12709#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12710#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12711#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12712#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12713
12714/****************** Bit definition for TIM_CCMR2 register *******************/
12715#define TIM_CCMR2_CC3S_Pos (0U)
12716#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12717#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12718#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12719#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12720
12721#define TIM_CCMR2_OC3FE_Pos (2U)
12722#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12723#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12724#define TIM_CCMR2_OC3PE_Pos (3U)
12725#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12726#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12727
12728#define TIM_CCMR2_OC3M_Pos (4U)
12729#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
12730#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12731#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
12732#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
12733#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
12734
12735#define TIM_CCMR2_OC3CE_Pos (7U)
12736#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12737#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12738
12739#define TIM_CCMR2_CC4S_Pos (8U)
12740#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12741#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12742#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12743#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12744
12745#define TIM_CCMR2_OC4FE_Pos (10U)
12746#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12747#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12748#define TIM_CCMR2_OC4PE_Pos (11U)
12749#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12750#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12751
12752#define TIM_CCMR2_OC4M_Pos (12U)
12753#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
12754#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12755#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
12756#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
12757#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
12758
12759#define TIM_CCMR2_OC4CE_Pos (15U)
12760#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12761#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12762
12763/*----------------------------------------------------------------------------*/
12764
12765#define TIM_CCMR2_IC3PSC_Pos (2U)
12766#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12767#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12768#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12769#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12770
12771#define TIM_CCMR2_IC3F_Pos (4U)
12772#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12773#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12774#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12775#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12776#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12777#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12778
12779#define TIM_CCMR2_IC4PSC_Pos (10U)
12780#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12781#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12782#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12783#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12784
12785#define TIM_CCMR2_IC4F_Pos (12U)
12786#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12787#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12788#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12789#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12790#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12791#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12792
12793/******************* Bit definition for TIM_CCER register *******************/
12794#define TIM_CCER_CC1E_Pos (0U)
12795#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12796#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12797#define TIM_CCER_CC1P_Pos (1U)
12798#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12799#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12800#define TIM_CCER_CC1NE_Pos (2U)
12801#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12802#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12803#define TIM_CCER_CC1NP_Pos (3U)
12804#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12805#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12806#define TIM_CCER_CC2E_Pos (4U)
12807#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12808#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12809#define TIM_CCER_CC2P_Pos (5U)
12810#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12811#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12812#define TIM_CCER_CC2NE_Pos (6U)
12813#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12814#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12815#define TIM_CCER_CC2NP_Pos (7U)
12816#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12817#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12818#define TIM_CCER_CC3E_Pos (8U)
12819#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12820#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12821#define TIM_CCER_CC3P_Pos (9U)
12822#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12823#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12824#define TIM_CCER_CC3NE_Pos (10U)
12825#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12826#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12827#define TIM_CCER_CC3NP_Pos (11U)
12828#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12829#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12830#define TIM_CCER_CC4E_Pos (12U)
12831#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12832#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12833#define TIM_CCER_CC4P_Pos (13U)
12834#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12835#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12836#define TIM_CCER_CC4NP_Pos (15U)
12837#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12838#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12839
12840/******************* Bit definition for TIM_CNT register ********************/
12841#define TIM_CNT_CNT_Pos (0U)
12842#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12843#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12844
12845/******************* Bit definition for TIM_PSC register ********************/
12846#define TIM_PSC_PSC_Pos (0U)
12847#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12848#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12849
12850/******************* Bit definition for TIM_ARR register ********************/
12851#define TIM_ARR_ARR_Pos (0U)
12852#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12853#define TIM_ARR_ARR TIM_ARR_ARR_Msk
12854
12855/******************* Bit definition for TIM_RCR register ********************/
12856#define TIM_RCR_REP_Pos (0U)
12857#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
12858#define TIM_RCR_REP TIM_RCR_REP_Msk
12859
12860/******************* Bit definition for TIM_CCR1 register *******************/
12861#define TIM_CCR1_CCR1_Pos (0U)
12862#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12863#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12864
12865/******************* Bit definition for TIM_CCR2 register *******************/
12866#define TIM_CCR2_CCR2_Pos (0U)
12867#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12868#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12869
12870/******************* Bit definition for TIM_CCR3 register *******************/
12871#define TIM_CCR3_CCR3_Pos (0U)
12872#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12873#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12874
12875/******************* Bit definition for TIM_CCR4 register *******************/
12876#define TIM_CCR4_CCR4_Pos (0U)
12877#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12878#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12879
12880/******************* Bit definition for TIM_BDTR register *******************/
12881#define TIM_BDTR_DTG_Pos (0U)
12882#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12883#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12884#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12885#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12886#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12887#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12888#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12889#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12890#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12891#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12892
12893#define TIM_BDTR_LOCK_Pos (8U)
12894#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12895#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12896#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12897#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12898
12899#define TIM_BDTR_OSSI_Pos (10U)
12900#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12901#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12902#define TIM_BDTR_OSSR_Pos (11U)
12903#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12904#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12905#define TIM_BDTR_BKE_Pos (12U)
12906#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12907#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12908#define TIM_BDTR_BKP_Pos (13U)
12909#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12910#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12911#define TIM_BDTR_AOE_Pos (14U)
12912#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12913#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12914#define TIM_BDTR_MOE_Pos (15U)
12915#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12916#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12917
12918/******************* Bit definition for TIM_DCR register ********************/
12919#define TIM_DCR_DBA_Pos (0U)
12920#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12921#define TIM_DCR_DBA TIM_DCR_DBA_Msk
12922#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12923#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12924#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12925#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12926#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12927
12928#define TIM_DCR_DBL_Pos (8U)
12929#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12930#define TIM_DCR_DBL TIM_DCR_DBL_Msk
12931#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12932#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12933#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12934#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12935#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12936
12937/******************* Bit definition for TIM_DMAR register *******************/
12938#define TIM_DMAR_DMAB_Pos (0U)
12939#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12940#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12941
12942/******************* Bit definition for TIM_OR register *********************/
12943#define TIM_OR_TI1_RMP_Pos (0U)
12944#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
12945#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
12946#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
12947#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
12948
12949#define TIM_OR_TI4_RMP_Pos (6U)
12950#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12951#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12952#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12953#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12954#define TIM_OR_ITR1_RMP_Pos (10U)
12955#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12956#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12957#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12958#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12959
12960/******************************************************************************/
12961/* */
12962/* Low Power Timer (LPTIM) */
12963/* */
12964/******************************************************************************/
12965/****************** Bit definition for LPTIM_ISR register *******************/
12966#define LPTIM_ISR_CMPM_Pos (0U)
12967#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
12968#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
12969#define LPTIM_ISR_ARRM_Pos (1U)
12970#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
12971#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
12972#define LPTIM_ISR_EXTTRIG_Pos (2U)
12973#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
12974#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
12975#define LPTIM_ISR_CMPOK_Pos (3U)
12976#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
12977#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
12978#define LPTIM_ISR_ARROK_Pos (4U)
12979#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
12980#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
12981#define LPTIM_ISR_UP_Pos (5U)
12982#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
12983#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
12984#define LPTIM_ISR_DOWN_Pos (6U)
12985#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
12986#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
12987
12988/****************** Bit definition for LPTIM_ICR register *******************/
12989#define LPTIM_ICR_CMPMCF_Pos (0U)
12990#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
12991#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
12992#define LPTIM_ICR_ARRMCF_Pos (1U)
12993#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
12994#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
12995#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
12996#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
12997#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
12998#define LPTIM_ICR_CMPOKCF_Pos (3U)
12999#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
13000#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
13001#define LPTIM_ICR_ARROKCF_Pos (4U)
13002#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
13003#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
13004#define LPTIM_ICR_UPCF_Pos (5U)
13005#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
13006#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
13007#define LPTIM_ICR_DOWNCF_Pos (6U)
13008#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
13009#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
13010
13011/****************** Bit definition for LPTIM_IER register ********************/
13012#define LPTIM_IER_CMPMIE_Pos (0U)
13013#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
13014#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
13015#define LPTIM_IER_ARRMIE_Pos (1U)
13016#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
13017#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
13018#define LPTIM_IER_EXTTRIGIE_Pos (2U)
13019#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
13020#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
13021#define LPTIM_IER_CMPOKIE_Pos (3U)
13022#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
13023#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
13024#define LPTIM_IER_ARROKIE_Pos (4U)
13025#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
13026#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
13027#define LPTIM_IER_UPIE_Pos (5U)
13028#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
13029#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
13030#define LPTIM_IER_DOWNIE_Pos (6U)
13031#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
13032#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
13033
13034/****************** Bit definition for LPTIM_CFGR register *******************/
13035#define LPTIM_CFGR_CKSEL_Pos (0U)
13036#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
13037#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
13038
13039#define LPTIM_CFGR_CKPOL_Pos (1U)
13040#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
13041#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
13042#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
13043#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
13044
13045#define LPTIM_CFGR_CKFLT_Pos (3U)
13046#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
13047#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
13048#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
13049#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
13050
13051#define LPTIM_CFGR_TRGFLT_Pos (6U)
13052#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
13053#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
13054#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
13055#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
13056
13057#define LPTIM_CFGR_PRESC_Pos (9U)
13058#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
13059#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
13060#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
13061#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
13062#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
13063
13064#define LPTIM_CFGR_TRIGSEL_Pos (13U)
13065#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
13066#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
13067#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
13068#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
13069#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
13070
13071#define LPTIM_CFGR_TRIGEN_Pos (17U)
13072#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
13073#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
13074#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
13075#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
13076
13077#define LPTIM_CFGR_TIMOUT_Pos (19U)
13078#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
13079#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
13080#define LPTIM_CFGR_WAVE_Pos (20U)
13081#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
13082#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
13083#define LPTIM_CFGR_WAVPOL_Pos (21U)
13084#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
13085#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
13086#define LPTIM_CFGR_PRELOAD_Pos (22U)
13087#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
13088#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
13089#define LPTIM_CFGR_COUNTMODE_Pos (23U)
13090#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
13091#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
13092#define LPTIM_CFGR_ENC_Pos (24U)
13093#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
13094#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
13095
13096/****************** Bit definition for LPTIM_CR register ********************/
13097#define LPTIM_CR_ENABLE_Pos (0U)
13098#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
13099#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
13100#define LPTIM_CR_SNGSTRT_Pos (1U)
13101#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
13102#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
13103#define LPTIM_CR_CNTSTRT_Pos (2U)
13104#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
13105#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
13106
13107/****************** Bit definition for LPTIM_CMP register *******************/
13108#define LPTIM_CMP_CMP_Pos (0U)
13109#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
13110#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
13111
13112/****************** Bit definition for LPTIM_ARR register *******************/
13113#define LPTIM_ARR_ARR_Pos (0U)
13114#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
13115#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
13116
13117/****************** Bit definition for LPTIM_CNT register *******************/
13118#define LPTIM_CNT_CNT_Pos (0U)
13119#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
13120#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
13121
13122/****************** Bit definition for LPTIM_OR register *******************/
13123#define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
13124#define LPTIM_OR_LPT_IN1_RMP_Msk (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13125#define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk
13126#define LPTIM_OR_LPT_IN1_RMP_0 (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13127#define LPTIM_OR_LPT_IN1_RMP_1 (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13128#define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
13129#define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1UL << LPTIM_OR_TIM1_ITR2_RMP_Pos)
13130#define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk
13131#define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
13132#define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM5_ITR1_RMP_Pos)
13133#define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk
13134#define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
13135#define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM9_ITR1_RMP_Pos)
13136#define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk
13137
13138/* Legacy Defines */
13139#define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
13140#define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
13141#define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
13142
13143
13144/******************************************************************************/
13145/* */
13146/* Universal Synchronous Asynchronous Receiver Transmitter */
13147/* */
13148/******************************************************************************/
13149/******************* Bit definition for USART_SR register *******************/
13150#define USART_SR_PE_Pos (0U)
13151#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
13152#define USART_SR_PE USART_SR_PE_Msk
13153#define USART_SR_FE_Pos (1U)
13154#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
13155#define USART_SR_FE USART_SR_FE_Msk
13156#define USART_SR_NE_Pos (2U)
13157#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
13158#define USART_SR_NE USART_SR_NE_Msk
13159#define USART_SR_ORE_Pos (3U)
13160#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
13161#define USART_SR_ORE USART_SR_ORE_Msk
13162#define USART_SR_IDLE_Pos (4U)
13163#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
13164#define USART_SR_IDLE USART_SR_IDLE_Msk
13165#define USART_SR_RXNE_Pos (5U)
13166#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
13167#define USART_SR_RXNE USART_SR_RXNE_Msk
13168#define USART_SR_TC_Pos (6U)
13169#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
13170#define USART_SR_TC USART_SR_TC_Msk
13171#define USART_SR_TXE_Pos (7U)
13172#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
13173#define USART_SR_TXE USART_SR_TXE_Msk
13174#define USART_SR_LBD_Pos (8U)
13175#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
13176#define USART_SR_LBD USART_SR_LBD_Msk
13177#define USART_SR_CTS_Pos (9U)
13178#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
13179#define USART_SR_CTS USART_SR_CTS_Msk
13180
13181/******************* Bit definition for USART_DR register *******************/
13182#define USART_DR_DR_Pos (0U)
13183#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
13184#define USART_DR_DR USART_DR_DR_Msk
13185
13186/****************** Bit definition for USART_BRR register *******************/
13187#define USART_BRR_DIV_Fraction_Pos (0U)
13188#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
13189#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
13190#define USART_BRR_DIV_Mantissa_Pos (4U)
13191#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
13192#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
13193
13194/****************** Bit definition for USART_CR1 register *******************/
13195#define USART_CR1_SBK_Pos (0U)
13196#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
13197#define USART_CR1_SBK USART_CR1_SBK_Msk
13198#define USART_CR1_RWU_Pos (1U)
13199#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
13200#define USART_CR1_RWU USART_CR1_RWU_Msk
13201#define USART_CR1_RE_Pos (2U)
13202#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
13203#define USART_CR1_RE USART_CR1_RE_Msk
13204#define USART_CR1_TE_Pos (3U)
13205#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
13206#define USART_CR1_TE USART_CR1_TE_Msk
13207#define USART_CR1_IDLEIE_Pos (4U)
13208#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
13209#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
13210#define USART_CR1_RXNEIE_Pos (5U)
13211#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
13212#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
13213#define USART_CR1_TCIE_Pos (6U)
13214#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
13215#define USART_CR1_TCIE USART_CR1_TCIE_Msk
13216#define USART_CR1_TXEIE_Pos (7U)
13217#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
13218#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
13219#define USART_CR1_PEIE_Pos (8U)
13220#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
13221#define USART_CR1_PEIE USART_CR1_PEIE_Msk
13222#define USART_CR1_PS_Pos (9U)
13223#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
13224#define USART_CR1_PS USART_CR1_PS_Msk
13225#define USART_CR1_PCE_Pos (10U)
13226#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
13227#define USART_CR1_PCE USART_CR1_PCE_Msk
13228#define USART_CR1_WAKE_Pos (11U)
13229#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
13230#define USART_CR1_WAKE USART_CR1_WAKE_Msk
13231#define USART_CR1_M_Pos (12U)
13232#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
13233#define USART_CR1_M USART_CR1_M_Msk
13234#define USART_CR1_UE_Pos (13U)
13235#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
13236#define USART_CR1_UE USART_CR1_UE_Msk
13237#define USART_CR1_OVER8_Pos (15U)
13238#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
13239#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
13240
13241/****************** Bit definition for USART_CR2 register *******************/
13242#define USART_CR2_ADD_Pos (0U)
13243#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
13244#define USART_CR2_ADD USART_CR2_ADD_Msk
13245#define USART_CR2_LBDL_Pos (5U)
13246#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
13247#define USART_CR2_LBDL USART_CR2_LBDL_Msk
13248#define USART_CR2_LBDIE_Pos (6U)
13249#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
13250#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
13251#define USART_CR2_LBCL_Pos (8U)
13252#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
13253#define USART_CR2_LBCL USART_CR2_LBCL_Msk
13254#define USART_CR2_CPHA_Pos (9U)
13255#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
13256#define USART_CR2_CPHA USART_CR2_CPHA_Msk
13257#define USART_CR2_CPOL_Pos (10U)
13258#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
13259#define USART_CR2_CPOL USART_CR2_CPOL_Msk
13260#define USART_CR2_CLKEN_Pos (11U)
13261#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
13262#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
13263
13264#define USART_CR2_STOP_Pos (12U)
13265#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
13266#define USART_CR2_STOP USART_CR2_STOP_Msk
13267#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
13268#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
13269
13270#define USART_CR2_LINEN_Pos (14U)
13271#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
13272#define USART_CR2_LINEN USART_CR2_LINEN_Msk
13273
13274/****************** Bit definition for USART_CR3 register *******************/
13275#define USART_CR3_EIE_Pos (0U)
13276#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
13277#define USART_CR3_EIE USART_CR3_EIE_Msk
13278#define USART_CR3_IREN_Pos (1U)
13279#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
13280#define USART_CR3_IREN USART_CR3_IREN_Msk
13281#define USART_CR3_IRLP_Pos (2U)
13282#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
13283#define USART_CR3_IRLP USART_CR3_IRLP_Msk
13284#define USART_CR3_HDSEL_Pos (3U)
13285#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
13286#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
13287#define USART_CR3_NACK_Pos (4U)
13288#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
13289#define USART_CR3_NACK USART_CR3_NACK_Msk
13290#define USART_CR3_SCEN_Pos (5U)
13291#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
13292#define USART_CR3_SCEN USART_CR3_SCEN_Msk
13293#define USART_CR3_DMAR_Pos (6U)
13294#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
13295#define USART_CR3_DMAR USART_CR3_DMAR_Msk
13296#define USART_CR3_DMAT_Pos (7U)
13297#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
13298#define USART_CR3_DMAT USART_CR3_DMAT_Msk
13299#define USART_CR3_RTSE_Pos (8U)
13300#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
13301#define USART_CR3_RTSE USART_CR3_RTSE_Msk
13302#define USART_CR3_CTSE_Pos (9U)
13303#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
13304#define USART_CR3_CTSE USART_CR3_CTSE_Msk
13305#define USART_CR3_CTSIE_Pos (10U)
13306#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
13307#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
13308#define USART_CR3_ONEBIT_Pos (11U)
13309#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
13310#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
13311
13312/****************** Bit definition for USART_GTPR register ******************/
13313#define USART_GTPR_PSC_Pos (0U)
13314#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
13315#define USART_GTPR_PSC USART_GTPR_PSC_Msk
13316#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
13317#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
13318#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
13319#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
13320#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
13321#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
13322#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
13323#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
13324
13325#define USART_GTPR_GT_Pos (8U)
13326#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
13327#define USART_GTPR_GT USART_GTPR_GT_Msk
13328
13329/******************************************************************************/
13330/* */
13331/* Window WATCHDOG */
13332/* */
13333/******************************************************************************/
13334/******************* Bit definition for WWDG_CR register ********************/
13335#define WWDG_CR_T_Pos (0U)
13336#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
13337#define WWDG_CR_T WWDG_CR_T_Msk
13338#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
13339#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
13340#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
13341#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
13342#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
13343#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
13344#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
13345/* Legacy defines */
13346#define WWDG_CR_T0 WWDG_CR_T_0
13347#define WWDG_CR_T1 WWDG_CR_T_1
13348#define WWDG_CR_T2 WWDG_CR_T_2
13349#define WWDG_CR_T3 WWDG_CR_T_3
13350#define WWDG_CR_T4 WWDG_CR_T_4
13351#define WWDG_CR_T5 WWDG_CR_T_5
13352#define WWDG_CR_T6 WWDG_CR_T_6
13353
13354#define WWDG_CR_WDGA_Pos (7U)
13355#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
13356#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
13357
13358/******************* Bit definition for WWDG_CFR register *******************/
13359#define WWDG_CFR_W_Pos (0U)
13360#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
13361#define WWDG_CFR_W WWDG_CFR_W_Msk
13362#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
13363#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
13364#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
13365#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
13366#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
13367#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
13368#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
13369/* Legacy defines */
13370#define WWDG_CFR_W0 WWDG_CFR_W_0
13371#define WWDG_CFR_W1 WWDG_CFR_W_1
13372#define WWDG_CFR_W2 WWDG_CFR_W_2
13373#define WWDG_CFR_W3 WWDG_CFR_W_3
13374#define WWDG_CFR_W4 WWDG_CFR_W_4
13375#define WWDG_CFR_W5 WWDG_CFR_W_5
13376#define WWDG_CFR_W6 WWDG_CFR_W_6
13377
13378#define WWDG_CFR_WDGTB_Pos (7U)
13379#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
13380#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
13381#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
13382#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
13383/* Legacy defines */
13384#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
13385#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
13386
13387#define WWDG_CFR_EWI_Pos (9U)
13388#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
13389#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
13390
13391/******************* Bit definition for WWDG_SR register ********************/
13392#define WWDG_SR_EWIF_Pos (0U)
13393#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
13394#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
13395
13396
13397/******************************************************************************/
13398/* */
13399/* DBG */
13400/* */
13401/******************************************************************************/
13402/******************** Bit definition for DBGMCU_IDCODE register *************/
13403#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13404#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
13405#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13406#define DBGMCU_IDCODE_REV_ID_Pos (16U)
13407#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
13408#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13409
13410/******************** Bit definition for DBGMCU_CR register *****************/
13411#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13412#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
13413#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13414#define DBGMCU_CR_DBG_STOP_Pos (1U)
13415#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
13416#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13417#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13418#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
13419#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13420#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13421#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
13422#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13423
13424#define DBGMCU_CR_TRACE_MODE_Pos (6U)
13425#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
13426#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13427#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
13428#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
13429
13430/******************** Bit definition for DBGMCU_APB1_FZ register ************/
13431#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13432#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
13433#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13434#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13435#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
13436#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13437#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13438#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
13439#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13440#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13441#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
13442#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13443#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13444#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
13445#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13446#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
13447#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
13448#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13449#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
13450#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
13451#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13452#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
13453#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
13454#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13455#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
13456#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
13457#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13458#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
13459#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos)
13460#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
13461#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
13462#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
13463#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13464#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
13465#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
13466#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13467#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
13468#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
13469#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13470#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
13471#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
13472#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13473#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
13474#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
13475#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13476#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
13477#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
13478#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13479#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
13480#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
13481#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
13482#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
13483#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
13484#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13485#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
13486#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
13487#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
13488#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
13489#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos)
13490#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
13491
13492/******************** Bit definition for DBGMCU_APB2_FZ register ************/
13493#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
13494#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
13495#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13496#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
13497#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
13498#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13499#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
13500#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
13501#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13502#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
13503#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
13504#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
13505#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
13506#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
13507#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
13508
13509/******************************************************************************/
13510/* */
13511/* USB_OTG */
13512/* */
13513/******************************************************************************/
13514/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13515#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13516#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13517#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13518#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13519#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13520#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13521#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
13522#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
13523#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
13524#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
13525#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
13526#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
13527#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
13528#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
13529#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
13530#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
13531#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
13532#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
13533#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
13534#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
13535#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
13536#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
13537#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
13538#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
13539#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13540#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13541#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13542#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13543#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13544#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13545#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13546#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13547#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13548#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13549#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13550#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13551#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
13552#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
13553#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
13554#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13555#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13556#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13557#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13558#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13559#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13560#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13561#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13562#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13563#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
13564#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
13565#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
13566#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
13567#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
13568#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
13569
13570/******************** Bit definition forUSB_OTG_HCFG register ********************/
13571
13572#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13573#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13574#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13575#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13576#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13577#define USB_OTG_HCFG_FSLSS_Pos (2U)
13578#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13579#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13580
13581/******************** Bit definition for USB_OTG_DCFG register ********************/
13582
13583#define USB_OTG_DCFG_DSPD_Pos (0U)
13584#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13585#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13586#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13587#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13588#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13589#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13590#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13591
13592#define USB_OTG_DCFG_DAD_Pos (4U)
13593#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13594#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13595#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13596#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13597#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13598#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13599#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13600#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13601#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13602
13603#define USB_OTG_DCFG_PFIVL_Pos (11U)
13604#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13605#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13606#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13607#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13608
13609#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
13610#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
13611#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
13612
13613#define USB_OTG_DCFG_ERRATIM_Pos (15U)
13614#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
13615#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
13616
13617#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13618#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13619#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13620#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13621#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13622
13623/******************** Bit definition for USB_OTG_PCGCR register ********************/
13624#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13625#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13626#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13627#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13628#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13629#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13630#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13631#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13632#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13633
13634/******************** Bit definition for USB_OTG_GOTGINT register ********************/
13635#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13636#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13637#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13638#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13639#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13640#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13641#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13642#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13643#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13644#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13645#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13646#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13647#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13648#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13649#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13650#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13651#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13652#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13653#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
13654#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
13655#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
13656
13657/******************** Bit definition for USB_OTG_DCTL register ********************/
13658#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13659#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13660#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13661#define USB_OTG_DCTL_SDIS_Pos (1U)
13662#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13663#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13664#define USB_OTG_DCTL_GINSTS_Pos (2U)
13665#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13666#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13667#define USB_OTG_DCTL_GONSTS_Pos (3U)
13668#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13669#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13670
13671#define USB_OTG_DCTL_TCTL_Pos (4U)
13672#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13673#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13674#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13675#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13676#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13677#define USB_OTG_DCTL_SGINAK_Pos (7U)
13678#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13679#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13680#define USB_OTG_DCTL_CGINAK_Pos (8U)
13681#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13682#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13683#define USB_OTG_DCTL_SGONAK_Pos (9U)
13684#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13685#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13686#define USB_OTG_DCTL_CGONAK_Pos (10U)
13687#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13688#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13689#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13690#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13691#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13692
13693/******************** Bit definition for USB_OTG_HFIR register ********************/
13694#define USB_OTG_HFIR_FRIVL_Pos (0U)
13695#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13696#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13697
13698/******************** Bit definition for USB_OTG_HFNUM register ********************/
13699#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13700#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13701#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13702#define USB_OTG_HFNUM_FTREM_Pos (16U)
13703#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13704#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13705
13706/******************** Bit definition for USB_OTG_DSTS register ********************/
13707#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13708#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13709#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13710
13711#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13712#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13713#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13714#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13715#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13716#define USB_OTG_DSTS_EERR_Pos (3U)
13717#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13718#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13719#define USB_OTG_DSTS_FNSOF_Pos (8U)
13720#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13721#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13722
13723/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13724#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13725#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13726#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13727#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13728#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13729#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13730#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13731#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13732#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13733#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13734#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13735#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13736#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13737#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13738#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13739#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13740#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13741#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13742#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13743#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13744
13745/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13746
13747#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13748#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13749#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13750#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13751#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13752#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13753#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13754#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13755#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13756#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13757#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13758#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13759#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13760#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13761#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13762#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13763#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13764#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13765#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13766#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13767#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13768#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13769#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13770#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13771#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13772#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13773#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
13774#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
13775#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13776#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
13777#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
13778#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13779#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
13780#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
13781#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13782#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
13783#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
13784#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13785#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
13786#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
13787#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13788#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
13789#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
13790#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13791#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
13792#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
13793#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13794#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
13795#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
13796#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13797#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
13798#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
13799#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13800#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
13801#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
13802#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13803#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
13804#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
13805#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13806#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
13807#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
13808
13809/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13810#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13811#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
13812#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
13813#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13814#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
13815#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
13816#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13817#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
13818#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
13819#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13820#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
13821#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
13822#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13823#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
13824#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
13825
13826
13827#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13828#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13829#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
13830#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13831#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13832#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13833#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13834#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13835#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13836#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
13837#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
13838#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13839#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
13840#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
13841
13842/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13843#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13844#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
13845#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
13846#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13847#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
13848#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
13849#define USB_OTG_DIEPMSK_TOM_Pos (3U)
13850#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
13851#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
13852#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13853#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
13854#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
13855#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13856#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
13857#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
13858#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13859#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
13860#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
13861#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13862#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
13863#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
13864#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
13865#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
13866#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
13867
13868/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
13869#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13870#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
13871#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
13872#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13873#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13874#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
13875#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13876#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13877#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13878#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13879#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13880#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13881#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13882#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13883
13884#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13885#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13886#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
13887#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13888#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13889#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13890#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13891#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13892#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13893#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13894#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13895
13896/******************** Bit definition for USB_OTG_HAINT register ********************/
13897#define USB_OTG_HAINT_HAINT_Pos (0U)
13898#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
13899#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
13900
13901/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
13902#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13903#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
13904#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
13905#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13906#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
13907#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
13908#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
13909#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
13910#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
13911#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13912#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
13913#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
13914#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13915#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
13916#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
13917#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13918#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
13919#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
13920#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13921#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
13922#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
13923#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13924#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
13925#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
13926#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13927#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
13928#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
13929#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
13930#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
13931#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
13932#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
13933#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
13934#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
13935#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
13936#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
13937#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
13938/******************** Bit definition for USB_OTG_GINTSTS register ********************/
13939#define USB_OTG_GINTSTS_CMOD_Pos (0U)
13940#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
13941#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
13942#define USB_OTG_GINTSTS_MMIS_Pos (1U)
13943#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
13944#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
13945#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13946#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
13947#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
13948#define USB_OTG_GINTSTS_SOF_Pos (3U)
13949#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
13950#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
13951#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13952#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
13953#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
13954#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13955#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
13956#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
13957#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13958#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
13959#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
13960#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13961#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
13962#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
13963#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13964#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
13965#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
13966#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13967#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
13968#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
13969#define USB_OTG_GINTSTS_USBRST_Pos (12U)
13970#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
13971#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
13972#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13973#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
13974#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
13975#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13976#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
13977#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
13978#define USB_OTG_GINTSTS_EOPF_Pos (15U)
13979#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
13980#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
13981#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13982#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
13983#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
13984#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13985#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
13986#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
13987#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13988#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
13989#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
13990#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13991#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
13992#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
13993#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13994#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
13995#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
13996#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
13997#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
13998#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
13999#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14000#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
14001#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
14002#define USB_OTG_GINTSTS_HCINT_Pos (25U)
14003#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
14004#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14005#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14006#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14007#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14008#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
14009#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
14010#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
14011#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14012#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14013#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14014#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14015#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14016#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14017#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14018#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14019#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14020#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14021#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14022#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14023
14024/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14025#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14026#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14027#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14028#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14029#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14030#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14031#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14032#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14033#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14034#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14035#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14036#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14037#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14038#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14039#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14040#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14041#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14042#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14043#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14044#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14045#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14046#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14047#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14048#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14049#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14050#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14051#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14052#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14053#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14054#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14055#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14056#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14057#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14058#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14059#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14060#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14061#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14062#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14063#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14064#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14065#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14066#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14067#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14068#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14069#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14070#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14071#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14072#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14073#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14074#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14075#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14076#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14077#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14078#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14079#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14080#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14081#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14082#define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
14083#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos)
14084#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk
14085#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14086#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14087#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14088#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14089#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14090#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14091#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14092#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14093#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14094#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
14095#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
14096#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
14097#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14098#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14099#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14100#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14101#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14102#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14103#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14104#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14105#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14106#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14107#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14108#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14109
14110/******************** Bit definition for USB_OTG_DAINT register ********************/
14111#define USB_OTG_DAINT_IEPINT_Pos (0U)
14112#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14113#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14114#define USB_OTG_DAINT_OEPINT_Pos (16U)
14115#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14116#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14117
14118/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14119#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14120#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14121#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14122
14123/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14124#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14125#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14126#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14127#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14128#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14129#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14130#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14131#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14132#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14133#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14134#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14135#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14136
14137/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14138#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14139#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14140#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14141#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14142#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14143#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14144
14145/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14146#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14147#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14148#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14149
14150/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14151#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14152#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14153#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14154
14155/******************** Bit definition for OTG register ********************/
14156#define USB_OTG_NPTXFSA_Pos (0U)
14157#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14158#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14159#define USB_OTG_NPTXFD_Pos (16U)
14160#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14161#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14162#define USB_OTG_TX0FSA_Pos (0U)
14163#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14164#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14165#define USB_OTG_TX0FD_Pos (16U)
14166#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14167#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14168
14169/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14170#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14171#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14172#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14173
14174/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14175#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14176#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14177#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14178
14179#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14180#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14181#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14182#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14183#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14184#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14185#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14186#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14187#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14188#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14189#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14190
14191#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14192#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14193#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14194#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14195#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14196#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14197#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14198#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14199#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14200#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14201
14202/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14203#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14204#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14205#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14206#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14207#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14208#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14209
14210#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14211#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14212#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14213#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14214#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14215#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14216#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14217#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14218#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14219#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14220#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14221#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14222#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14223#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14224#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14225
14226#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14227#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14228#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14229#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14230#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14231#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14232#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14233#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14234#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14235#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14236#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14237#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14238#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14239#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14240#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14241
14242/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14243#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14244#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14245#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14246
14247/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14248#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14249#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14250#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14251#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14252#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14253#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14254
14255/******************** Bit definition for USB_OTG_GCCFG register ********************/
14256#define USB_OTG_GCCFG_DCDET_Pos (0U)
14257#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
14258#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
14259#define USB_OTG_GCCFG_PDET_Pos (1U)
14260#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
14261#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
14262#define USB_OTG_GCCFG_SDET_Pos (2U)
14263#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
14264#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
14265#define USB_OTG_GCCFG_PS2DET_Pos (3U)
14266#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
14267#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
14268#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14269#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14270#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14271#define USB_OTG_GCCFG_BCDEN_Pos (17U)
14272#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
14273#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
14274#define USB_OTG_GCCFG_DCDEN_Pos (18U)
14275#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
14276#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
14277#define USB_OTG_GCCFG_PDEN_Pos (19U)
14278#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
14279#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
14280#define USB_OTG_GCCFG_SDEN_Pos (20U)
14281#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
14282#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
14283#define USB_OTG_GCCFG_VBDEN_Pos (21U)
14284#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
14285#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
14286
14287/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14288#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14289#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14290#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14291#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14292#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14293#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14294
14295/******************** Bit definition for USB_OTG_CID register ********************/
14296#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14297#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14298#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14299
14300/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14301#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14302#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
14303#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
14304#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14305#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
14306#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
14307#define USB_OTG_GLPMCFG_BESL_Pos (2U)
14308#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
14309#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
14310#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14311#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
14312#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
14313#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14314#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
14315#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
14316#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14317#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
14318#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
14319#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14320#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
14321#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
14322#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14323#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
14324#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
14325#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14326#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
14327#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
14328#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14329#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
14330#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
14331#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14332#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
14333#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
14334#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14335#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
14336#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
14337#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14338#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
14339#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
14340#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14341#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
14342#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
14343#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14344#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
14345#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
14346
14347/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14348#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14349#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14350#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14351#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14352#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14353#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14354#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14355#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14356#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14357#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14358#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14359#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14360#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14361#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14362#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14363#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14364#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14365#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14366#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14367#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14368#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14369#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14370#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14371#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14372#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14373#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14374#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14375
14376/******************** Bit definition for USB_OTG_HPRT register ********************/
14377#define USB_OTG_HPRT_PCSTS_Pos (0U)
14378#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14379#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14380#define USB_OTG_HPRT_PCDET_Pos (1U)
14381#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14382#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14383#define USB_OTG_HPRT_PENA_Pos (2U)
14384#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14385#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14386#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14387#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14388#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14389#define USB_OTG_HPRT_POCA_Pos (4U)
14390#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14391#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14392#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14393#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14394#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14395#define USB_OTG_HPRT_PRES_Pos (6U)
14396#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14397#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14398#define USB_OTG_HPRT_PSUSP_Pos (7U)
14399#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14400#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14401#define USB_OTG_HPRT_PRST_Pos (8U)
14402#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14403#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14404
14405#define USB_OTG_HPRT_PLSTS_Pos (10U)
14406#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14407#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14408#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14409#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14410#define USB_OTG_HPRT_PPWR_Pos (12U)
14411#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14412#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14413
14414#define USB_OTG_HPRT_PTCTL_Pos (13U)
14415#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14416#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14417#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14418#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14419#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14420#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14421
14422#define USB_OTG_HPRT_PSPD_Pos (17U)
14423#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14424#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14425#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14426#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14427
14428/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14429#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14430#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14431#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14432#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14433#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14434#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14435#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14436#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14437#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14438#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14439#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14440#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14441#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14442#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14443#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14444#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14445#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14446#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14447#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14448#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14449#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14450#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14451#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14452#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14453#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14454#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14455#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14456#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14457#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14458#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14459#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14460#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14461#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14462
14463/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14464#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14465#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14466#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14467#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14468#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14469#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14470
14471/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14472#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14473#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14474#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14475#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14476#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14477#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14478#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14479#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14480#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14481#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14482#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14483#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14484
14485#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14486#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14487#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14488#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14489#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14490#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14491#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14492#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14493
14494#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14495#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14496#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14497#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14498#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14499#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14500#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14501#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14502#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14503#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14504#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14505#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14506#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14507#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14508#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14509#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14510#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14511#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14512#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14513#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14514#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14515#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14516#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14517#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14518#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14519
14520/******************** Bit definition for USB_OTG_HCCHAR register ********************/
14521#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14522#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14523#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14524
14525#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14526#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14527#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14528#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14529#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14530#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14531#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14532#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14533#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14534#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14535#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14536#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14537#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14538
14539#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14540#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14541#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14542#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14543#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14544
14545#define USB_OTG_HCCHAR_MC_Pos (20U)
14546#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14547#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14548#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14549#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14550
14551#define USB_OTG_HCCHAR_DAD_Pos (22U)
14552#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14553#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14554#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14555#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14556#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14557#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14558#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14559#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14560#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14561#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14562#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14563#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14564#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14565#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14566#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14567#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14568#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14569#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14570
14571/******************** Bit definition for USB_OTG_HCSPLT register ********************/
14572
14573#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14574#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14575#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14576#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14577#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14578#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14579#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14580#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14581#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14582#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14583
14584#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14585#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14586#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14587#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14588#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14589#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14590#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14591#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14592#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14593#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14594
14595#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14596#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14597#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14598#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14599#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14600#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14601#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14602#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14603#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14604#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14605#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14606
14607/******************** Bit definition for USB_OTG_HCINT register ********************/
14608#define USB_OTG_HCINT_XFRC_Pos (0U)
14609#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14610#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14611#define USB_OTG_HCINT_CHH_Pos (1U)
14612#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14613#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14614#define USB_OTG_HCINT_AHBERR_Pos (2U)
14615#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14616#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14617#define USB_OTG_HCINT_STALL_Pos (3U)
14618#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14619#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14620#define USB_OTG_HCINT_NAK_Pos (4U)
14621#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14622#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14623#define USB_OTG_HCINT_ACK_Pos (5U)
14624#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14625#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14626#define USB_OTG_HCINT_NYET_Pos (6U)
14627#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14628#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14629#define USB_OTG_HCINT_TXERR_Pos (7U)
14630#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14631#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14632#define USB_OTG_HCINT_BBERR_Pos (8U)
14633#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14634#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14635#define USB_OTG_HCINT_FRMOR_Pos (9U)
14636#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14637#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14638#define USB_OTG_HCINT_DTERR_Pos (10U)
14639#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14640#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14641
14642/******************** Bit definition for USB_OTG_DIEPINT register ********************/
14643#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14644#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14645#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14646#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14647#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14648#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14649#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14650#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14651#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14652#define USB_OTG_DIEPINT_TOC_Pos (3U)
14653#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14654#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14655#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14656#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14657#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14658#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14659#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14660#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14661#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14662#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14663#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14664#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14665#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14666#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14667#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14668#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14669#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14670#define USB_OTG_DIEPINT_BNA_Pos (9U)
14671#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14672#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14673#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14674#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14675#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14676#define USB_OTG_DIEPINT_BERR_Pos (12U)
14677#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14678#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14679#define USB_OTG_DIEPINT_NAK_Pos (13U)
14680#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14681#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14682
14683/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14684#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14685#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14686#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14687#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14688#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14689#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14690#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14691#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14692#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14693#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14694#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14695#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14696#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14697#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14698#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14699#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14700#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14701#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14702#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14703#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14704#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14705#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14706#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14707#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14708#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14709#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14710#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14711#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14712#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14713#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14714#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14715#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14716#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14717
14718/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14719
14720#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14721#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14722#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14723#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14724#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14725#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14726#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14727#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14728#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14729/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14730#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14731#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14732#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14733#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14734#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14735#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14736#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14737#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14738#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14739#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14740#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14741#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14742#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14743#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14744
14745/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14746#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14747#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14748#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14749
14750/******************** Bit definition for USB_OTG_HCDMA register ********************/
14751#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14752#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14753#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14754
14755/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14756#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14757#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14758#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14759
14760/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14761#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14762#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14763#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14764#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14765#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14766#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14767
14768/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14769
14770#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14771#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14772#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14773#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14774#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14775#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14776#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14777#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14778#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14779#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14780#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14781#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14782#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14783#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14784#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14785#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14786#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14787#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14788#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14789#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14790#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14791#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14792#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14793#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14794#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14795#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14796#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14797#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14798#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14799#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14800#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14801#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14802#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14803#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14804#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14805#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14806#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14807#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14808
14809/******************** Bit definition for USB_OTG_DOEPINT register ********************/
14810#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14811#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14812#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14813#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14814#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14815#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14816#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14817#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14818#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14819#define USB_OTG_DOEPINT_STUP_Pos (3U)
14820#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14821#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14822#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14823#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14824#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14825#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14826#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14827#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14828#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14829#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14830#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14831#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14832#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14833#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14834#define USB_OTG_DOEPINT_NAK_Pos (13U)
14835#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14836#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14837#define USB_OTG_DOEPINT_NYET_Pos (14U)
14838#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14839#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14840#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14841#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14842#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14843/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14844
14845#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14846#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
14847#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
14848#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14849#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
14850#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
14851
14852#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14853#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14854#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
14855#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14856#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14857
14858/******************** Bit definition for PCGCCTL register ********************/
14859#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14860#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
14861#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
14862#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14863#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
14864#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
14865#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14866#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
14867#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
14868
14869/* Legacy define */
14870/******************** Bit definition for OTG register ********************/
14871#define USB_OTG_CHNUM_Pos (0U)
14872#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
14873#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
14874#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
14875#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
14876#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
14877#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
14878#define USB_OTG_BCNT_Pos (4U)
14879#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
14880#define USB_OTG_BCNT USB_OTG_BCNT_Msk
14881
14882#define USB_OTG_DPID_Pos (15U)
14883#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
14884#define USB_OTG_DPID USB_OTG_DPID_Msk
14885#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
14886#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
14887
14888#define USB_OTG_PKTSTS_Pos (17U)
14889#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
14890#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
14891#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
14892#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
14893#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
14894#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
14895
14896#define USB_OTG_EPNUM_Pos (0U)
14897#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
14898#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
14899#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
14900#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
14901#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
14902#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
14903
14904#define USB_OTG_FRMNUM_Pos (21U)
14905#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
14906#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
14907#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
14908#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
14909#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
14910#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
14914
14918
14922
14923/******************************* ADC Instances ********************************/
14924#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14925
14926#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14927
14928/******************************* CAN Instances ********************************/
14929#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14930 ((INSTANCE) == CAN2) || \
14931 ((INSTANCE) == CAN3))
14932
14933/****************************** DFSDM Instances *******************************/
14934#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
14935 ((INSTANCE) == DFSDM1_Filter1) || \
14936 ((INSTANCE) == DFSDM2_Filter0) || \
14937 ((INSTANCE) == DFSDM2_Filter1) || \
14938 ((INSTANCE) == DFSDM2_Filter2) || \
14939 ((INSTANCE) == DFSDM2_Filter3))
14940
14941#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
14942 ((INSTANCE) == DFSDM1_Channel1) || \
14943 ((INSTANCE) == DFSDM1_Channel2) || \
14944 ((INSTANCE) == DFSDM1_Channel3) || \
14945 ((INSTANCE) == DFSDM2_Channel0) || \
14946 ((INSTANCE) == DFSDM2_Channel1) || \
14947 ((INSTANCE) == DFSDM2_Channel2) || \
14948 ((INSTANCE) == DFSDM2_Channel3) || \
14949 ((INSTANCE) == DFSDM2_Channel4) || \
14950 ((INSTANCE) == DFSDM2_Channel5) || \
14951 ((INSTANCE) == DFSDM2_Channel6) || \
14952 ((INSTANCE) == DFSDM2_Channel7))
14953/******************************* CRC Instances ********************************/
14954#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14955
14956/******************************* DAC Instances ********************************/
14957#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14958
14959
14960/******************************** DMA Instances *******************************/
14961#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14962 ((INSTANCE) == DMA1_Stream1) || \
14963 ((INSTANCE) == DMA1_Stream2) || \
14964 ((INSTANCE) == DMA1_Stream3) || \
14965 ((INSTANCE) == DMA1_Stream4) || \
14966 ((INSTANCE) == DMA1_Stream5) || \
14967 ((INSTANCE) == DMA1_Stream6) || \
14968 ((INSTANCE) == DMA1_Stream7) || \
14969 ((INSTANCE) == DMA2_Stream0) || \
14970 ((INSTANCE) == DMA2_Stream1) || \
14971 ((INSTANCE) == DMA2_Stream2) || \
14972 ((INSTANCE) == DMA2_Stream3) || \
14973 ((INSTANCE) == DMA2_Stream4) || \
14974 ((INSTANCE) == DMA2_Stream5) || \
14975 ((INSTANCE) == DMA2_Stream6) || \
14976 ((INSTANCE) == DMA2_Stream7))
14977
14978/******************************* GPIO Instances *******************************/
14979#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14980 ((INSTANCE) == GPIOB) || \
14981 ((INSTANCE) == GPIOC) || \
14982 ((INSTANCE) == GPIOD) || \
14983 ((INSTANCE) == GPIOE) || \
14984 ((INSTANCE) == GPIOF) || \
14985 ((INSTANCE) == GPIOG) || \
14986 ((INSTANCE) == GPIOH))
14987
14988/******************************** I2C Instances *******************************/
14989#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14990 ((INSTANCE) == I2C2) || \
14991 ((INSTANCE) == I2C3))
14992
14993/******************************* SMBUS Instances ******************************/
14994#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
14995
14996/******************************** I2S Instances *******************************/
14997#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14998 ((INSTANCE) == SPI3))
14999
15000#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15001 ((INSTANCE) == SPI2) || \
15002 ((INSTANCE) == SPI3) || \
15003 ((INSTANCE) == SPI4) || \
15004 ((INSTANCE) == SPI5))
15005
15006/*************************** I2S Extended Instances ***************************/
15007#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
15008 ((INSTANCE) == I2S3ext))
15009/* Legacy Defines */
15010#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
15011
15012/******************************* LPTIM Instances ******************************/
15013#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
15014
15015/******************************* RNG Instances ********************************/
15016#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15017
15018/****************************** RTC Instances *********************************/
15019#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15020
15021
15022/******************************** SPI Instances *******************************/
15023
15024#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15025 ((INSTANCE) == SPI2) || \
15026 ((INSTANCE) == SPI3) || \
15027 ((INSTANCE) == SPI4) || \
15028 ((INSTANCE) == SPI5))
15029
15030
15031/*************************** SPI Extended Instances ***************************/
15032#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
15033 ((INSTANCE) == SPI2) || \
15034 ((INSTANCE) == SPI3) || \
15035 ((INSTANCE) == SPI4) || \
15036 ((INSTANCE) == SPI5) || \
15037 ((INSTANCE) == I2S2ext) || \
15038 ((INSTANCE) == I2S3ext))
15039/******************************* SAI Instances ********************************/
15040#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
15041 ((PERIPH) == SAI1_Block_B))
15042/****************** TIM Instances : All supported instances *******************/
15043#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15044 ((INSTANCE) == TIM2) || \
15045 ((INSTANCE) == TIM3) || \
15046 ((INSTANCE) == TIM4) || \
15047 ((INSTANCE) == TIM5) || \
15048 ((INSTANCE) == TIM6) || \
15049 ((INSTANCE) == TIM7) || \
15050 ((INSTANCE) == TIM8) || \
15051 ((INSTANCE) == TIM9) || \
15052 ((INSTANCE) == TIM10)|| \
15053 ((INSTANCE) == TIM11)|| \
15054 ((INSTANCE) == TIM12)|| \
15055 ((INSTANCE) == TIM13)|| \
15056 ((INSTANCE) == TIM14))
15057
15058/************* TIM Instances : at least 1 capture/compare channel *************/
15059#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15060 ((INSTANCE) == TIM2) || \
15061 ((INSTANCE) == TIM3) || \
15062 ((INSTANCE) == TIM4) || \
15063 ((INSTANCE) == TIM5) || \
15064 ((INSTANCE) == TIM8) || \
15065 ((INSTANCE) == TIM9) || \
15066 ((INSTANCE) == TIM10) || \
15067 ((INSTANCE) == TIM11) || \
15068 ((INSTANCE) == TIM12) || \
15069 ((INSTANCE) == TIM13) || \
15070 ((INSTANCE) == TIM14))
15071
15072/************ TIM Instances : at least 2 capture/compare channels *************/
15073#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15074 ((INSTANCE) == TIM2) || \
15075 ((INSTANCE) == TIM3) || \
15076 ((INSTANCE) == TIM4) || \
15077 ((INSTANCE) == TIM5) || \
15078 ((INSTANCE) == TIM8) || \
15079 ((INSTANCE) == TIM9) || \
15080 ((INSTANCE) == TIM12))
15081
15082/************ TIM Instances : at least 3 capture/compare channels *************/
15083#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15084 ((INSTANCE) == TIM2) || \
15085 ((INSTANCE) == TIM3) || \
15086 ((INSTANCE) == TIM4) || \
15087 ((INSTANCE) == TIM5) || \
15088 ((INSTANCE) == TIM8))
15089
15090/************ TIM Instances : at least 4 capture/compare channels *************/
15091#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15092 ((INSTANCE) == TIM2) || \
15093 ((INSTANCE) == TIM3) || \
15094 ((INSTANCE) == TIM4) || \
15095 ((INSTANCE) == TIM5) || \
15096 ((INSTANCE) == TIM8))
15097
15098/******************** TIM Instances : Advanced-control timers *****************/
15099#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15100 ((INSTANCE) == TIM8))
15101
15102/******************* TIM Instances : Timer input XOR function *****************/
15103#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15104 ((INSTANCE) == TIM2) || \
15105 ((INSTANCE) == TIM3) || \
15106 ((INSTANCE) == TIM4) || \
15107 ((INSTANCE) == TIM5) || \
15108 ((INSTANCE) == TIM8))
15109
15110/****************** TIM Instances : DMA requests generation (UDE) *************/
15111#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15112 ((INSTANCE) == TIM2) || \
15113 ((INSTANCE) == TIM3) || \
15114 ((INSTANCE) == TIM4) || \
15115 ((INSTANCE) == TIM5) || \
15116 ((INSTANCE) == TIM6) || \
15117 ((INSTANCE) == TIM7) || \
15118 ((INSTANCE) == TIM8))
15119
15120/************ TIM Instances : DMA requests generation (CCxDE) *****************/
15121#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15122 ((INSTANCE) == TIM2) || \
15123 ((INSTANCE) == TIM3) || \
15124 ((INSTANCE) == TIM4) || \
15125 ((INSTANCE) == TIM5) || \
15126 ((INSTANCE) == TIM8))
15127
15128/************ TIM Instances : DMA requests generation (COMDE) *****************/
15129#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15130 ((INSTANCE) == TIM2) || \
15131 ((INSTANCE) == TIM3) || \
15132 ((INSTANCE) == TIM4) || \
15133 ((INSTANCE) == TIM5) || \
15134 ((INSTANCE) == TIM8))
15135
15136/******************** TIM Instances : DMA burst feature ***********************/
15137#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15138 ((INSTANCE) == TIM2) || \
15139 ((INSTANCE) == TIM3) || \
15140 ((INSTANCE) == TIM4) || \
15141 ((INSTANCE) == TIM5) || \
15142 ((INSTANCE) == TIM8))
15143
15144/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15145#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15146 ((INSTANCE) == TIM2) || \
15147 ((INSTANCE) == TIM3) || \
15148 ((INSTANCE) == TIM4) || \
15149 ((INSTANCE) == TIM5) || \
15150 ((INSTANCE) == TIM6) || \
15151 ((INSTANCE) == TIM7) || \
15152 ((INSTANCE) == TIM8))
15153
15154/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15155#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15156 ((INSTANCE) == TIM2) || \
15157 ((INSTANCE) == TIM3) || \
15158 ((INSTANCE) == TIM4) || \
15159 ((INSTANCE) == TIM5) || \
15160 ((INSTANCE) == TIM8) || \
15161 ((INSTANCE) == TIM9) || \
15162 ((INSTANCE) == TIM12))
15163/********************** TIM Instances : 32 bit Counter ************************/
15164#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15165 ((INSTANCE) == TIM5))
15166
15167/***************** TIM Instances : external trigger input available ************/
15168#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15169 ((INSTANCE) == TIM2) || \
15170 ((INSTANCE) == TIM3) || \
15171 ((INSTANCE) == TIM4) || \
15172 ((INSTANCE) == TIM5) || \
15173 ((INSTANCE) == TIM8))
15174
15175/****************** TIM Instances : remapping capability **********************/
15176#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15177 ((INSTANCE) == TIM5) || \
15178 ((INSTANCE) == TIM11))
15179
15180/******************* TIM Instances : output(s) available **********************/
15181#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15182 ((((INSTANCE) == TIM1) && \
15183 (((CHANNEL) == TIM_CHANNEL_1) || \
15184 ((CHANNEL) == TIM_CHANNEL_2) || \
15185 ((CHANNEL) == TIM_CHANNEL_3) || \
15186 ((CHANNEL) == TIM_CHANNEL_4))) \
15187 || \
15188 (((INSTANCE) == TIM2) && \
15189 (((CHANNEL) == TIM_CHANNEL_1) || \
15190 ((CHANNEL) == TIM_CHANNEL_2) || \
15191 ((CHANNEL) == TIM_CHANNEL_3) || \
15192 ((CHANNEL) == TIM_CHANNEL_4))) \
15193 || \
15194 (((INSTANCE) == TIM3) && \
15195 (((CHANNEL) == TIM_CHANNEL_1) || \
15196 ((CHANNEL) == TIM_CHANNEL_2) || \
15197 ((CHANNEL) == TIM_CHANNEL_3) || \
15198 ((CHANNEL) == TIM_CHANNEL_4))) \
15199 || \
15200 (((INSTANCE) == TIM4) && \
15201 (((CHANNEL) == TIM_CHANNEL_1) || \
15202 ((CHANNEL) == TIM_CHANNEL_2) || \
15203 ((CHANNEL) == TIM_CHANNEL_3) || \
15204 ((CHANNEL) == TIM_CHANNEL_4))) \
15205 || \
15206 (((INSTANCE) == TIM5) && \
15207 (((CHANNEL) == TIM_CHANNEL_1) || \
15208 ((CHANNEL) == TIM_CHANNEL_2) || \
15209 ((CHANNEL) == TIM_CHANNEL_3) || \
15210 ((CHANNEL) == TIM_CHANNEL_4))) \
15211 || \
15212 (((INSTANCE) == TIM8) && \
15213 (((CHANNEL) == TIM_CHANNEL_1) || \
15214 ((CHANNEL) == TIM_CHANNEL_2) || \
15215 ((CHANNEL) == TIM_CHANNEL_3) || \
15216 ((CHANNEL) == TIM_CHANNEL_4))) \
15217 || \
15218 (((INSTANCE) == TIM9) && \
15219 (((CHANNEL) == TIM_CHANNEL_1) || \
15220 ((CHANNEL) == TIM_CHANNEL_2))) \
15221 || \
15222 (((INSTANCE) == TIM10) && \
15223 (((CHANNEL) == TIM_CHANNEL_1))) \
15224 || \
15225 (((INSTANCE) == TIM11) && \
15226 (((CHANNEL) == TIM_CHANNEL_1))) \
15227 || \
15228 (((INSTANCE) == TIM12) && \
15229 (((CHANNEL) == TIM_CHANNEL_1) || \
15230 ((CHANNEL) == TIM_CHANNEL_2))) \
15231 || \
15232 (((INSTANCE) == TIM13) && \
15233 (((CHANNEL) == TIM_CHANNEL_1))) \
15234 || \
15235 (((INSTANCE) == TIM14) && \
15236 (((CHANNEL) == TIM_CHANNEL_1))))
15237
15238/************ TIM Instances : complementary output(s) available ***************/
15239#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15240 ((((INSTANCE) == TIM1) && \
15241 (((CHANNEL) == TIM_CHANNEL_1) || \
15242 ((CHANNEL) == TIM_CHANNEL_2) || \
15243 ((CHANNEL) == TIM_CHANNEL_3))) \
15244 || \
15245 (((INSTANCE) == TIM8) && \
15246 (((CHANNEL) == TIM_CHANNEL_1) || \
15247 ((CHANNEL) == TIM_CHANNEL_2) || \
15248 ((CHANNEL) == TIM_CHANNEL_3))))
15249
15250/****************** TIM Instances : supporting counting mode selection ********/
15251#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15252 ((INSTANCE) == TIM2) || \
15253 ((INSTANCE) == TIM3) || \
15254 ((INSTANCE) == TIM4) || \
15255 ((INSTANCE) == TIM5) || \
15256 ((INSTANCE) == TIM8))
15257
15258/****************** TIM Instances : supporting clock division *****************/
15259#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15260 ((INSTANCE) == TIM2) || \
15261 ((INSTANCE) == TIM3) || \
15262 ((INSTANCE) == TIM4) || \
15263 ((INSTANCE) == TIM5) || \
15264 ((INSTANCE) == TIM8) || \
15265 ((INSTANCE) == TIM9) || \
15266 ((INSTANCE) == TIM10)|| \
15267 ((INSTANCE) == TIM11)|| \
15268 ((INSTANCE) == TIM12)|| \
15269 ((INSTANCE) == TIM13)|| \
15270 ((INSTANCE) == TIM14))
15271
15272/****************** TIM Instances : supporting commutation event generation ***/
15273#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15274 ((INSTANCE) == TIM8))
15275
15276
15277/****************** TIM Instances : supporting OCxREF clear *******************/
15278#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15279 ((INSTANCE) == TIM2) || \
15280 ((INSTANCE) == TIM3) || \
15281 ((INSTANCE) == TIM4) || \
15282 ((INSTANCE) == TIM5) || \
15283 ((INSTANCE) == TIM8))
15284
15285/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15286#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15287 ((INSTANCE) == TIM2) || \
15288 ((INSTANCE) == TIM3) || \
15289 ((INSTANCE) == TIM4) || \
15290 ((INSTANCE) == TIM5) || \
15291 ((INSTANCE) == TIM8) || \
15292 ((INSTANCE) == TIM9) || \
15293 ((INSTANCE) == TIM12))
15294
15295/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15296#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15297 ((INSTANCE) == TIM2) || \
15298 ((INSTANCE) == TIM3) || \
15299 ((INSTANCE) == TIM4) || \
15300 ((INSTANCE) == TIM5) || \
15301 ((INSTANCE) == TIM8))
15302
15303/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15304#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15305 ((INSTANCE) == TIM2) || \
15306 ((INSTANCE) == TIM3) || \
15307 ((INSTANCE) == TIM4) || \
15308 ((INSTANCE) == TIM5) || \
15309 ((INSTANCE) == TIM8) || \
15310 ((INSTANCE) == TIM9) || \
15311 ((INSTANCE) == TIM12))
15312
15313/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15314#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15315 ((INSTANCE) == TIM2) || \
15316 ((INSTANCE) == TIM3) || \
15317 ((INSTANCE) == TIM4) || \
15318 ((INSTANCE) == TIM5) || \
15319 ((INSTANCE) == TIM8) || \
15320 ((INSTANCE) == TIM9) || \
15321 ((INSTANCE) == TIM12))
15322
15323/****************** TIM Instances : supporting repetition counter *************/
15324#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15325 ((INSTANCE) == TIM8))
15326
15327/****************** TIM Instances : supporting encoder interface **************/
15328#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15329 ((INSTANCE) == TIM2) || \
15330 ((INSTANCE) == TIM3) || \
15331 ((INSTANCE) == TIM4) || \
15332 ((INSTANCE) == TIM5) || \
15333 ((INSTANCE) == TIM8) || \
15334 ((INSTANCE) == TIM9))
15335/****************** TIM Instances : supporting Hall sensor interface **********/
15336#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15337 ((INSTANCE) == TIM2) || \
15338 ((INSTANCE) == TIM3) || \
15339 ((INSTANCE) == TIM4) || \
15340 ((INSTANCE) == TIM5) || \
15341 ((INSTANCE) == TIM8))
15342/****************** TIM Instances : supporting the break function *************/
15343#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15344 ((INSTANCE) == TIM8))
15345
15346/******************** USART Instances : Synchronous mode **********************/
15347#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15348 ((INSTANCE) == USART2) || \
15349 ((INSTANCE) == USART3) || \
15350 ((INSTANCE) == USART6))
15351
15352/******************** UART Instances : Half-Duplex mode **********************/
15353#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15354 ((INSTANCE) == USART2) || \
15355 ((INSTANCE) == USART3) || \
15356 ((INSTANCE) == UART4) || \
15357 ((INSTANCE) == UART5) || \
15358 ((INSTANCE) == USART6) || \
15359 ((INSTANCE) == UART7) || \
15360 ((INSTANCE) == UART8) || \
15361 ((INSTANCE) == UART9) || \
15362 ((INSTANCE) == UART10))
15363
15364/* Legacy defines */
15365#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15366
15367/****************** UART Instances : Hardware Flow control ********************/
15368#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15369 ((INSTANCE) == USART2) || \
15370 ((INSTANCE) == USART3) || \
15371 ((INSTANCE) == USART6))
15372/******************** UART Instances : LIN mode **********************/
15373#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15374
15375/********************* UART Instances : Smart card mode ***********************/
15376#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15377 ((INSTANCE) == USART2) || \
15378 ((INSTANCE) == USART3) || \
15379 ((INSTANCE) == USART6))
15380
15381/*********************** UART Instances : IRDA mode ***************************/
15382#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15383 ((INSTANCE) == USART2) || \
15384 ((INSTANCE) == USART3) || \
15385 ((INSTANCE) == UART4) || \
15386 ((INSTANCE) == UART5) || \
15387 ((INSTANCE) == USART6) || \
15388 ((INSTANCE) == UART7) || \
15389 ((INSTANCE) == UART8) || \
15390 ((INSTANCE) == UART9) || \
15391 ((INSTANCE) == UART10))
15392
15393/*********************** PCD Instances ****************************************/
15394#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15395
15396/*********************** HCD Instances ****************************************/
15397#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15398
15399/****************************** SDIO Instances ********************************/
15400#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15401
15402/****************************** IWDG Instances ********************************/
15403#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15404
15405/****************************** WWDG Instances ********************************/
15406#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15407
15408
15409/***************************** FMPI2C Instances *******************************/
15410#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15411#define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
15412
15413/****************************** QSPI Instances ********************************/
15414#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15415/****************************** USB Exported Constants ************************/
15416#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
15417#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15418#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15419#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15420
15421/*
15422 * @brief Specific devices reset values definitions
15423 */
15424#define RCC_PLLCFGR_RST_VALUE 0x24003010U
15425#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
15426
15427#define RCC_MAX_FREQUENCY 100000000U
15428#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
15429#define RCC_MAX_FREQUENCY_SCALE2 84000000U
15430#define RCC_MAX_FREQUENCY_SCALE3 64000000U
15431#define RCC_PLLVCO_OUTPUT_MIN 100000000U
15432#define RCC_PLLVCO_INPUT_MIN 950000U
15433#define RCC_PLLVCO_INPUT_MAX 2100000U
15434#define RCC_PLLVCO_OUTPUT_MAX 432000000U
15435
15436#define RCC_PLLN_MIN_VALUE 50U
15437#define RCC_PLLN_MAX_VALUE 432U
15438
15439#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
15440#define FLASH_SCALE1_LATENCY2_FREQ 64000000U
15441#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
15442
15443#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
15444#define FLASH_SCALE2_LATENCY2_FREQ 64000000U
15445
15446#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
15447#define FLASH_SCALE3_LATENCY2_FREQ 64000000U
15448
15449
15453
15457
15461
15462#ifdef __cplusplus
15463}
15464#endif /* __cplusplus */
15465
15466#endif /* __STM32F413xx_H */
#define __IO
#define RESERVED(N, T)
Definition core_ca.h:179
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
@ PendSV_IRQn
Definition stm32f401xc.h:74
@ DFSDM2_FLT1_IRQn
@ EXTI2_IRQn
Definition stm32f401xc.h:85
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
@ UART10_IRQn
@ SDIO_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
@ DMA2_Stream0_IRQn
@ DMA2_Stream6_IRQn
@ UART7_IRQn
@ I2C1_ER_IRQn
@ UART9_IRQn
@ I2C2_EV_IRQn
@ CAN3_SCE_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
@ SAI1_IRQn
@ TIM4_IRQn
@ TIM2_IRQn
@ DFSDM2_FLT0_IRQn
@ DMA2_Stream7_IRQn
@ TIM8_BRK_TIM12_IRQn
@ USART2_IRQn
@ DMA2_Stream3_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
@ ADC_IRQn
Definition stm32f401xc.h:95
@ SPI3_IRQn
@ SPI2_IRQn
@ DFSDM2_FLT2_IRQn
@ TIM7_IRQn
@ UART8_IRQn
@ CAN2_SCE_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
@ CAN3_RX0_IRQn
@ TIM6_DAC_IRQn
@ I2C2_ER_IRQn
@ QUADSPI_IRQn
@ DFSDM1_FLT0_IRQn
@ TIM8_CC_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
@ SysTick_IRQn
Definition stm32f401xc.h:75
@ I2C3_ER_IRQn
@ FMPI2C1_ER_IRQn
@ CAN3_TX_IRQn
@ DFSDM2_FLT3_IRQn
@ I2C3_EV_IRQn
@ CAN2_RX0_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
@ SPI5_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
@ RNG_IRQn
@ FLASH_IRQn
Definition stm32f401xc.h:81
@ DMA2_Stream5_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
@ I2C1_EV_IRQn
@ TIM3_IRQn
@ DMA2_Stream1_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
@ EXTI15_10_IRQn
@ SPI4_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
@ LPTIM1_IRQn
@ OTG_FS_IRQn
@ OTG_FS_WKUP_IRQn
@ FPU_IRQn
@ TIM8_UP_TIM13_IRQn
@ USART6_IRQn
@ SPI1_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
@ CAN2_RX1_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
@ EXTI4_IRQn
Definition stm32f401xc.h:87
@ DMA2_Stream2_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
@ UART5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
@ CAN3_RX1_IRQn
@ USART1_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
@ UART4_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
@ DMA2_Stream4_IRQn
@ FMPI2C1_EV_IRQn
@ TIM5_IRQn
@ DMA1_Stream7_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
@ TIM1_CC_IRQn
@ CAN2_TX_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
@ USART3_IRQn
@ RTC_Alarm_IRQn
@ DFSDM1_FLT1_IRQn
Analog to Digital Converter.
Controller Area Network FIFOMailBox.
Controller Area Network FilterRegister.
Controller Area Network TxMailBox.
Controller Area Network.
CRC calculation unit.
Digital to Analog Converter.
Debug MCU.
DFSDM channel configuration registers.
DFSDM module registers.
DMA Controller.
External Interrupt/Event Controller.
FLASH Registers.
Inter-integrated Circuit Interface.
Flexible Static Memory Controller.
Flexible Static Memory Controller Bank1E.
General Purpose I/O.
Inter-integrated Circuit Interface.
Independent WATCHDOG.
Power Control.
QUAD Serial Peripheral Interface.
Reset and Clock Control.
Real-Time Clock.
__IO uint32_t DR
__IO uint32_t CLRFR
__IO uint32_t CR1
__IO uint32_t SLOTR
__IO uint32_t FRCR
__IO uint32_t IMR
__IO uint32_t SR
__IO uint32_t CR2
Serial Audio Interface.
__IO uint32_t GCR
SD host Interface.
Serial Peripheral Interface.
System configuration controller.
__IO uint32_t CFGR
uint32_t RESERVED1[2]
__IO uint32_t MCHDLYCR
Universal Synchronous Asynchronous Receiver Transmitter.
USB_OTG_device_Registers.
USB_OTG_Core_Registers.
USB_OTG_Host_Channel_Specific_Registers.
USB_OTG_Host_Mode_Register_Structures.
USB_OTG_IN_Endpoint-Specific_Register.
USB_OTG_OUT_Endpoint-Specific_Registers.
Window WATCHDOG.
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.